* Patch by Gleb Natapov, 14 Sep 2003:

  enable watchdog support for all MPC824x boards that have a watchdog

* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the
  "Non-octet Aligned Frame" errors we see at 100 Mbps

* Patch by Sharad Gupta, 14 Sep 2003:
  fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])

4 files changed, 27 insertions, 8 deletions

diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index 06dd56fc504..634698bf68d 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -427,7 +427,11 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 			/*
 			 * Set the auto-negotiation advertisement register bits
 			 */
+#ifndef CONFIG_FEC_10MBIT
 			miiphy_write(phyAddr, 0x4, 0x01e1);
+#else
+			miiphy_write(phyAddr, 0x4, 0x061);/* Advertise 10FDX */
+#endif
 
 			/*
 			 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index a890a6d0a73..a54c5f4b2a9 100644
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -48,9 +48,11 @@ static int mpc5200_read_config_dword(struct pci_controller *hose,
 {
 	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
 	eieio();
+	udelay(10);
 	*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
 	eieio();
 	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+	udelay(10);
 	return 0;
 }
 
@@ -59,9 +61,11 @@ static int mpc5200_write_config_dword(struct pci_controller *hose,
 {
 	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
 	eieio();
+	udelay(10);
 	out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
 	eieio();
 	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+	udelay(10);
 	return 0;
 }
 
diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index 216c1c88f39..0557909e19d 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -382,6 +382,14 @@ init_5xxx_core:
 	mtspr	DBAT2L, r0
 	mtspr	DBAT3U, r0
 	mtspr	DBAT3L, r0
+	mtspr	DBAT4U, r0
+	mtspr	DBAT4L, r0
+	mtspr	DBAT5U, r0
+	mtspr	DBAT5L, r0
+	mtspr	DBAT6U, r0
+	mtspr	DBAT6L, r0
+	mtspr	DBAT7U, r0
+	mtspr	DBAT7L, r0
 	mtspr	IBAT0U, r0
 	mtspr	IBAT0L, r0
 	mtspr	IBAT1U, r0
@@ -390,6 +398,14 @@ init_5xxx_core:
 	mtspr	IBAT2L, r0
 	mtspr	IBAT3U, r0
 	mtspr	IBAT3L, r0
+	mtspr	IBAT4U, r0
+	mtspr	IBAT4L, r0
+	mtspr	IBAT5U, r0
+	mtspr	IBAT5L, r0
+	mtspr	IBAT6U, r0
+	mtspr	IBAT6L, r0
+	mtspr	IBAT7U, r0
+	mtspr	IBAT7L, r0
 	SYNC
 
 	/* invalidate all tlb's						*/
diff --git a/cpu/mpc824x/interrupts.c b/cpu/mpc824x/interrupts.c
index 753575f8687..825857b0548 100644
--- a/cpu/mpc824x/interrupts.c
+++ b/cpu/mpc824x/interrupts.c
@@ -27,6 +27,7 @@
 #include <asm/processor.h>
 #include <asm/pci_io.h>
 #include <commproc.h>
+#include <watchdog.h>
 #include "drivers/epic.h"
 
 /****************************************************************************/
@@ -149,15 +150,9 @@ void timer_interrupt (struct pt_regs *regs)
 
 	timestamp++;
 
-#if defined(CONFIG_WATCHDOG)
+#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
 	if ((timestamp % (CFG_HZ / 2)) == 0) {
-#if defined(CONFIG_OXC)
-		{
-			extern void oxc_wdt_reset (void);
-
-			oxc_wdt_reset ();
-		}
-#endif
+		WATCHDOG_RESET ();
 	}
 #endif							/* CONFIG_WATCHDOG */
 #if defined(CONFIG_SHOW_ACTIVITY) && defined(CONFIG_OXC)