diff options
| author | Simon Glass | 2023-05-04 16:55:03 -0600 |
|---|---|---|
| committer | Bin Meng | 2023-05-11 10:25:29 +0800 |
| commit | b6b33d104ddca734a0348f7e7794ccb1709f8df8 (patch) | |
| tree | 354f9d78a676e58b3cbdbae40f31460f6ab749e2 /doc/board | |
| parent | b21626d4cb4ed258755b64e36baedb5e040ebf20 (diff) | |
x86: coreboot: Document how to enable the debug UART
This is not obvious so add a little note about how it works.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'doc/board')
| -rw-r--r-- | doc/board/coreboot/coreboot.rst | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index 4a5f101cad2..0fe95af56d2 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -71,3 +71,32 @@ Memory map (typically redirects to 7ab10030 or similar) 500 Location of coreboot sysinfo table, used during startup ========== ================================================================== + + +Debug UART +---------- + +It is possible to enable the debug UART with coreboot. To do this, use the +info from the cbsysinfo command to locate the UART base. For example:: + + => cbsysinfo + ... + Serial I/O port: 00000000 + base : 00000000 + pointer : 767b51bc + type : 2 + base : fe03e000 + baud : 0d115200 + regwidth : 4 + input_hz : 0d1843200 + PCI addr : 00000010 + ... + +Here you can see that the UART base is fe03e000, regwidth is 4 (1 << 2) and the +input clock is 1843200. So you can add the following CONFIG options:: + + CONFIG_DEBUG_UART=y + CONFIG_DEBUG_UART_BASE=fe03e000 + CONFIG_DEBUG_UART_CLOCK=1843200 + CONFIG_DEBUG_UART_SHIFT=2 + CONFIG_DEBUG_UART_ANNOUNCE=y |