diff options
| author | Patrick Delaunay | 2019-01-30 13:07:06 +0100 |
|---|---|---|
| committer | Tom Rini | 2019-02-09 07:50:57 -0500 |
| commit | bbd108a08225b1239b1ec1c10e8131fba6a3a95a (patch) | |
| tree | 3324114ed3c850227bebde0f28d258b303028b50 /doc/device-tree-bindings | |
| parent | e74b74c52876d776dda7a7ee5e2a8d555eaa5c4f (diff) | |
clk: stm32mp1: correctly handle Clock Spreading Generator
To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'doc/device-tree-bindings')
| -rw-r--r-- | doc/device-tree-bindings/clock/st,stm32mp1.txt | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt index 6a9397e1054..ffcf8cd31dc 100644 --- a/doc/device-tree-bindings/clock/st,stm32mp1.txt +++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt @@ -132,15 +132,15 @@ Optional Properties: frac = < 0x810 >; }; st,pll@1 { - cfg = < 1 43 1 0 0 PQR(0,1,1)>; - csg = <10 20 1>; + cfg = < 1 43 1 0 0 PQR(0,1,1) >; + csg = < 10 20 1 >; }; st,pll@2 { - cfg = < 2 85 3 13 3 0>; - csg = <10 20 SSCG_MODE_CENTER_SPREAD>; + cfg = < 2 85 3 13 3 0 >; + csg = < 10 20 SSCG_MODE_CENTER_SPREAD >; }; st,pll@3 { - cfg = < 2 78 4 7 9 3>; + cfg = < 2 78 4 7 9 3 >; }; st,pkcs = < CLK_STGEN_HSE |