diff options
| author | Mateusz Kulikowski | 2016-03-31 23:12:16 +0200 |
|---|---|---|
| committer | Tom Rini | 2016-04-01 17:18:08 -0400 |
| commit | 9d11d12a16d12caae7f9418322485392a5583423 (patch) | |
| tree | b19cbba507955ca19b454c93efc5a8b4373a6f1f /doc | |
| parent | 81a87e189456be131e4c95a8a0b6b4c4c52e0175 (diff) | |
mmc: Add support for Qualcomm SDHCI controller
Add support for SD/eMMC controller present on some Qualcomm Snapdragon
devices. This controller implements SDHCI 2.0 interface but requires
vendor-specific initialization.
Driver works in PIO mode as ADMA is not supported by U-Boot (yet).
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/device-tree-bindings/mmc/msm_sdhci.txt | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/mmc/msm_sdhci.txt b/doc/device-tree-bindings/mmc/msm_sdhci.txt new file mode 100644 index 00000000000..08a290c6693 --- /dev/null +++ b/doc/device-tree-bindings/mmc/msm_sdhci.txt @@ -0,0 +1,25 @@ +Qualcomm Snapdragon SDHCI controller + +Required properties: +- compatible : "qcom,sdhci-msm-v4" +- reg: Base address and length of registers: + - Host controller registers (SDHCI) + - SD Core registers +- clock: interface clock (must accept SD bus clock as a frequency) + +Optional properties: +- index: If there is more than one controller - controller index (required + by generic SDHCI code). +- bus_width: Width of SD/eMMC bus (default 4) +- clock-frequency: Frequency of SD/eMMC bus (default 400 kHz) + +Example: + +sdhci@07864000 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x7864900 0x11c 0x7864000 0x800>; + index = <0x1>; + bus-width = <0x4>; + clock = <&clkc 1>; + clock-frequency = <200000000>; +}; |