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authorJagan Teki2019-02-28 00:26:59 +0530
committerJagan Teki2019-03-09 13:16:35 +0530
commitaefc0b7a60b9147b79b7a735c045e28daba712f1 (patch)
tree0790e0977f61242f1c686b58bc20e2a9dad0eaa4 /doc
parent68620c9698f109c1f001f80d282138a5c67cabef (diff)
clk: sunxi: h3: Implement EPHY CLK and RESET
EPHY CLK and RESET is available in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respective clock and reset reg and bits. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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