diff options
| author | Abdellatif El Khlifi | 2023-04-17 10:11:55 +0100 |
|---|---|---|
| committer | Tom Rini | 2023-04-27 17:01:14 -0400 |
| commit | cc89b7cf419223a746ab3cfc5741a19cd40ebabe (patch) | |
| tree | fda0dbc390c9de9bff060019e61a9f08b326e960 /doc | |
| parent | 4b6d114d6d30dafd18c27fb00608b2f6038ac5ff (diff) | |
sandbox64: add support for NVMXIP QSPI
enable NVMXIP QSPI for sandbox 64-bit
Adding two NVM XIP QSPI storage devices.
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/develop/driver-model/nvmxip.rst | 2 | ||||
| -rw-r--r-- | doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/doc/develop/driver-model/nvmxip.rst b/doc/develop/driver-model/nvmxip.rst index 09afdbcccf5..e85dc220b9c 100644 --- a/doc/develop/driver-model/nvmxip.rst +++ b/doc/develop/driver-model/nvmxip.rst @@ -56,7 +56,7 @@ The implementation is generic and can be used by different platforms. Supported hardware -------------------------------- -Any 64-bit plaform. +Any plaform supporting readq(). Configuration ---------------------- diff --git a/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt b/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt index cc60e9efdcd..882728d5413 100644 --- a/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt +++ b/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt @@ -16,7 +16,7 @@ If a platform has its own driver, please provide your own compatible string. 2) - reg = <0x0 0x08000000 0x0 0x00200000>; + reg = /bits/ 64 <0x08000000 0x00200000>; The start address and size of the flash device. The values give here are an example (when the cell size is 2). @@ -43,14 +43,14 @@ Example of multiple flash devices nvmxip-qspi1@08000000 { compatible = "nvmxip,qspi"; - reg = <0x0 0x08000000 0x0 0x00200000>; + reg = /bits/ 64 <0x08000000 0x00200000>; lba_shift = <9>; lba = <4096>; }; nvmxip-qspi2@08200000 { compatible = "nvmxip,qspi"; - reg = <0x0 0x08200000 0x0 0x00100000>; + reg = /bits/ 64 <0x08200000 0x00100000>; lba_shift = <9>; lba = <2048>; }; |