diff options
| author | Zhengxun | 2021-06-11 15:10:48 +0000 |
|---|---|---|
| committer | Michal Simek | 2021-06-23 09:48:35 +0200 |
| commit | 2b157d8127804d879d2624e1ed79085950957476 (patch) | |
| tree | 405e0a7fb56c430f700fc8e65825d3866d7634f4 /drivers/clk/Kconfig | |
| parent | 4d3de8abff4dae76569751265fe8b636ac51138b (diff) | |
clk: zynq: Add clock wizard driver
The Clocking Wizard IP supports clock circuits customized
to your clocking requirements. The wizard support for
dynamically reconfiguring the clocking primitives for
Multiply, Divide, Phase Shift/Offset, or Duty Cycle.
Limited by U-Boot clk uclass without set_phase API, this
patch only provides set_rate to modify the frequency.
Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/clk/Kconfig')
| -rw-r--r-- | drivers/clk/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 40a5a5dd883..a0ac661f28f 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -128,6 +128,17 @@ config CLK_ZYNQ This clock driver adds support for clock related settings for Zynq platform. +config CLK_XLNX_CLKWZRD + bool "Xilinx Clocking Wizard" + depends on CLK + help + Support for the Xilinx Clocking Wizard IP core clock generator. + The wizard support for dynamically reconfiguring the clocking + primitives for Multiply, Divide, Phase Shift/Offset, or Duty + Cycle. Limited by U-Boot clk uclass without set_phase API and + set_duty_cycle API, this driver only supports set_rate to modify + the frequency. + config CLK_ZYNQMP bool "Enable clock driver support for ZynqMP" depends on ARCH_ZYNQMP |