diff options
| author | Ley Foon Tan | 2020-07-10 20:55:20 +0800 |
|---|---|---|
| committer | Ley Foon Tan | 2020-10-09 17:53:10 +0800 |
| commit | 36162a8eb8962e9447e9ad03b5103a3a66228476 (patch) | |
| tree | 7afcddf2e81d9dd4c25b2484a367f043043b3e6b /drivers/clk/altera | |
| parent | a58d86db46456c4e14d4d140e419c4c5999fb2f8 (diff) | |
clk: agilex: Add NAND clock support
Add get nand_clk and nand_x clock support.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Diffstat (limited to 'drivers/clk/altera')
| -rw-r--r-- | drivers/clk/altera/clk-agilex.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 9927ada201f..d7402999ef5 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -533,7 +533,10 @@ static ulong socfpga_clk_get_rate(struct clk *clk) case AGILEX_EMAC2_CLK: return clk_get_emac_clk_hz(plat, clk->id); case AGILEX_USB_CLK: + case AGILEX_NAND_X_CLK: return clk_get_l4_mp_clk_hz(plat); + case AGILEX_NAND_CLK: + return clk_get_l4_mp_clk_hz(plat) / 4; default: return -ENXIO; } |