diff options
| author | Simon Glass | 2020-12-03 16:55:21 -0700 |
|---|---|---|
| committer | Simon Glass | 2020-12-13 16:51:09 -0700 |
| commit | d1998a9fde0a917d6496299f6a97b6bccfdc6724 (patch) | |
| tree | 1931d0c875e829620180bf383722c1a69bd1a951 /drivers/clk/altera | |
| parent | c69cda25c9b59e53a6bc8969ada58942549f5b5d (diff) | |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat()
This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/clk/altera')
| -rw-r--r-- | drivers/clk/altera/clk-agilex.c | 4 | ||||
| -rw-r--r-- | drivers/clk/altera/clk-arria10.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index c67155c03f5..e0f43a264c5 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -628,7 +628,7 @@ static int socfpga_clk_probe(struct udevice *dev) return 0; } -static int socfpga_clk_ofdata_to_platdata(struct udevice *dev) +static int socfpga_clk_of_to_plat(struct udevice *dev) { struct socfpga_clk_platdata *plat = dev_get_plat(dev); fdt_addr_t addr; @@ -657,6 +657,6 @@ U_BOOT_DRIVER(socfpga_agilex_clk) = { .of_match = socfpga_clk_match, .ops = &socfpga_clk_ops, .probe = socfpga_clk_probe, - .ofdata_to_platdata = socfpga_clk_ofdata_to_platdata, + .of_to_plat = socfpga_clk_of_to_plat, .plat_auto = sizeof(struct socfpga_clk_platdata), }; diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c index 11f10c51028..e1e4876025d 100644 --- a/drivers/clk/altera/clk-arria10.c +++ b/drivers/clk/altera/clk-arria10.c @@ -319,7 +319,7 @@ static int socfpga_a10_clk_probe(struct udevice *dev) return 0; } -static int socfpga_a10_ofdata_to_platdata(struct udevice *dev) +static int socfpga_a10_of_to_plat(struct udevice *dev) { struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev); unsigned int divreg[3], gatereg[2]; @@ -357,7 +357,7 @@ U_BOOT_DRIVER(socfpga_a10_clk) = { .ops = &socfpga_a10_clk_ops, .bind = socfpga_a10_clk_bind, .probe = socfpga_a10_clk_probe, - .ofdata_to_platdata = socfpga_a10_ofdata_to_platdata, + .of_to_plat = socfpga_a10_of_to_plat, .plat_auto = sizeof(struct socfpga_a10_clk_platdata), }; |