diff options
| author | Conor Dooley | 2022-10-25 08:58:47 +0100 |
|---|---|---|
| committer | Leo Yu-Chi Liang | 2022-11-15 15:37:17 +0800 |
| commit | 88b697fb37432b95bd87525e718726607bdb2123 (patch) | |
| tree | b406040e16430ac1a14adc107b4f518847328d28 /drivers/clk/microchip/mpfs_clk.h | |
| parent | 32cfdd51630506393ca078aa36fa70248d549109 (diff) | |
clk: microchip: mpfs: fix periph clk parentage
Not all "periph" clocks are children of the AHB clock, some have the AXI
clock as their parent & the mtimer clock is derived from the external
reference clock directly. Stop assuming the AHB clock to be the parent
of all "periph" clocks and define their correct parents instead.
Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
Diffstat (limited to 'drivers/clk/microchip/mpfs_clk.h')
| -rw-r--r-- | drivers/clk/microchip/mpfs_clk.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/microchip/mpfs_clk.h b/drivers/clk/microchip/mpfs_clk.h index cb7d303e67a..72288cc971b 100644 --- a/drivers/clk/microchip/mpfs_clk.h +++ b/drivers/clk/microchip/mpfs_clk.h @@ -27,10 +27,10 @@ int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent); * mpfs_clk_register_periphs() - register peripheral clocks * * @base: base address of the mpfs system register. - * @parent: a pointer to parent clock. + * @dev: udevice representing the clock controller. * Return: zero on success, or a negative error code. */ -int mpfs_clk_register_periphs(void __iomem *base, struct clk *parent); +int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev); /** * divider_get_val() - get the clock divider value * |