Merge branch 'qcom-main' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon

Various minor fixes and improvements:

* Fix Qualcomm SPMI v5 support
* Move default environment to a file
* Add support for special pins (e.g ufs/mmc reset/data pins)
* IPQ moves to OF_UPSTREAM and receives some cleanup and MAINTAINERS
  changes
* Add a reset driver for devices without PSCI
* msm8916 USB clock improvements for mobile devices

2 files changed, 53 insertions, 0 deletions

diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index 41fe4d896a7..b5def55dbc2 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -16,6 +16,8 @@
 
 #include "clock-qcom.h"
 
+#define USB_HS_SYSTEM_CLK_CMD_RCGR	0x41010
+
 /* Clocks: (from CLK_CTL_BASE)  */
 #define GPLL0_STATUS			(0x2101C)
 #define APCS_GPLL_ENA_VOTE		(0x45000)
@@ -51,6 +53,11 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
 	.vote_bit = BIT(10),
 };
 
+static const struct gate_clk apq8016_clks[] = {
+	GATE_CLK(GCC_USB_HS_AHB_CLK,    0x41008, 0x00000001),
+	GATE_CLK(GCC_USB_HS_SYSTEM_CLK,	0x41004, 0x00000001),
+};
+
 /* SDHCI */
 static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
 {
@@ -116,13 +123,38 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate)
 	case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
 		apq8016_clk_init_uart(priv->base, clk->id);
 		return 7372800;
+	case GCC_USB_HS_SYSTEM_CLK:
+		if (rate != 80000000)
+			log_warning("Unexpected rate %ld requested for USB_HS_SYSTEM_CLK\n",
+				    rate);
+		clk_rcg_set_rate_mnd(priv->base, USB_HS_SYSTEM_CLK_CMD_RCGR,
+				     10, 0, 0, CFG_CLK_SRC_GPLL0, 0);
+		return rate;
 	default:
 		return 0;
 	}
 }
 
+static int apq8016_clk_enable(struct clk *clk)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	if (priv->data->num_clks < clk->id) {
+		log_warning("%s: unknown clk id %lu\n", __func__, clk->id);
+		return 0;
+	}
+
+	debug("%s: clk %s\n", __func__, apq8016_clks[clk->id].name);
+	qcom_gate_clk_en(priv, clk->id);
+
+	return 0;
+}
+
 static struct msm_clk_data apq8016_clk_data = {
 	.set_rate = apq8016_clk_set_rate,
+	.clks = apq8016_clks,
+	.num_clks = ARRAY_SIZE(apq8016_clks),
+	.enable = apq8016_clk_enable,
 };
 
 static const struct udevice_id gcc_apq8016_of_match[] = {
diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c
index 0e6d93b3d7c..9352ff46818 100644
--- a/drivers/clk/qcom/clock-ipq4019.c
+++ b/drivers/clk/qcom/clock-ipq4019.c
@@ -15,6 +15,12 @@
 
 #include "clock-qcom.h"
 
+/* I2C controller clock control registerss */
+#define BLSP1_QUP1_I2C_APPS_CBCR	(0x2008)
+#define BLSP1_QUP1_I2C_APPS_CMD_RCGR	(0x200C)
+#define BLSP1_QUP2_I2C_APPS_CBCR	(0x3010)
+#define BLSP1_QUP2_I2C_APPS_CMD_RCGR	(0x3000)
+
 static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)
 {
 	switch (clk->id) {
@@ -28,7 +34,22 @@ static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)
 
 static int ipq4019_clk_enable(struct clk *clk)
 {
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
 	switch (clk->id) {
+	case GCC_BLSP1_AHB_CLK:
+		/* This clock is already initialized by SBL1 */
+		return 0;
+	case GCC_BLSP1_QUP1_I2C_APPS_CLK:
+		clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR);
+		clk_rcg_set_rate(priv->base, BLSP1_QUP1_I2C_APPS_CMD_RCGR, 0,
+				 CFG_CLK_SRC_CXO);
+		return 0;
+	case GCC_BLSP1_QUP2_I2C_APPS_CLK:
+		clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR);
+		clk_rcg_set_rate(priv->base, BLSP1_QUP2_I2C_APPS_CMD_RCGR, 0,
+				 CFG_CLK_SRC_CXO);
+		return 0;
 	case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
 		/* This clock is already initialized by SBL1 */
 		return 0;