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authorMarek Vasut2019-03-18 05:38:08 +0100
committerMarek Vasut2019-03-25 20:26:53 +0100
commit4b135d54649eb79d5dfcd20feee82f6675c502c3 (patch)
treeecca034082e3f28ba44f1ae068c318f74623b0e4 /drivers/clk/renesas
parent45b01b462feedaecb28c3407a438a245c73fe6d0 (diff)
clk: renesas: Fix swapped div and mul in debug output on Gen2
The $div and $mul values were swapped in the debug output, fix this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/clk/renesas')
-rw-r--r--drivers/clk/renesas/clk-rcar-gen2.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index aedaab723bf..34abe784fdd 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -121,7 +121,7 @@ static ulong gen2_clk_get_rate(struct clk *clk)
case CLK_TYPE_FF:
rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
- debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
+ debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
__func__, __LINE__,
core->parent, core->mult, core->div, rate);
return rate;