diff options
| author | Jagan Teki | 2019-02-27 20:02:06 +0530 |
|---|---|---|
| committer | Jagan Teki | 2019-03-04 18:08:56 +0530 |
| commit | 82111469a5451adeb14413dc744c96f1bf13c758 (patch) | |
| tree | f6b6999f828ae5e3c1d1706b55b74d77f4d45edc /drivers/clk/sunxi/clk_v3s.c | |
| parent | 6cb6aa602b541d2b2f864c47b6a3f62e3eefe282 (diff) | |
clk: sunxi: Implement SPI clocks, resets
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
Allwinner SoCs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/clk/sunxi/clk_v3s.c')
| -rw-r--r-- | drivers/clk/sunxi/clk_v3s.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index c8a90278897..789ac72026b 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -16,12 +16,15 @@ static struct ccu_clk_gate v3s_gates[] = { [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), + [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), + [CLK_SPI0] = GATE(0x0a0, BIT(31)), + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), }; @@ -31,6 +34,7 @@ static struct ccu_reset v3s_resets[] = { [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), + [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), |