diff options
| author | Tom Rini | 2020-04-07 11:58:44 -0400 |
|---|---|---|
| committer | Tom Rini | 2020-04-07 17:13:35 -0400 |
| commit | 1f47e2aca42c2e51ff3a7754c717ee13f568c721 (patch) | |
| tree | eca6cb5e551dbb75c2328b1dba3e7a2b8a77d327 /drivers/clk | |
| parent | 2b18b89156335bf1f0d84f81d3597762bc48c61d (diff) | |
| parent | 895a7866c20cf6c01779b5a60fbf2770b88930a4 (diff) | |
Merge tag 'xilinx-for-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2020.07
common:
- Align ENV_FAT_INTERFACE
- Fix MAC address source print log
- Improve based autodetection code
xilinx:
- Enable netconsole
Microblaze:
- Setup default ENV_OFFSET/ENV_SECT_SIZE
Zynq:
- Multiple DT updates/fixes
- Use DEVICE_TREE environment variable for DTB selection
- Switch to single zynq configuration
- Enable NOR flash via DM
- Minor SPL print removal
- Enable i2c mux driver
ZynqMP:
- Print multiboot register
- Enable cache commands in mini mtest
- Multiple DT updates/fixes
- Fix firmware probing when driver is not enabled
- Specify 3rd backup RAM boot mode in SPL
- Add SPL support for zcu102 v1.1 and zcu111 revA
- Redesign debug uart enabling and psu_init delay
- Enable full u-boot run from EL3
- Enable u-boot.itb generation without ATF with U-Boot in EL3
Versal:
- Enable distro default
- Enable others SPI flashes
- Enable systems without DDR
Drivers:
- Gem:
- Flush memory after freeing
- Handle mdio bus separately
- Watchdog:
- Get rid of unused global data pointer
- Enable window watchdog timer
- Serial:
- Change reinitialization logic in zynq serial driver
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/renesas/clk-rcar-gen2.c | 3 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 7 |
2 files changed, 9 insertions, 1 deletions
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index 13111b341af..bfd7620dae1 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -291,7 +291,8 @@ int gen2_clk_probe(struct udevice *dev) if (ret < 0) return ret; - rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg"); + rst_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, ret, "reg", + 0, NULL, false); if (rst_base == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 865b80cc0fb..1f623765956 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -994,6 +994,13 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case DCLK_VOP1: ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); break; + case ACLK_VOP1: + case HCLK_VOP1: + /** + * assigned-clocks handling won't require for vopl, so + * return 0 to satisfy clk_set_defaults during device probe. + */ + return 0; case SCLK_DDRCLK: ret = rk3399_ddr_set_clk(priv->cru, rate); break; |