diff options
| author | Chanho Park | 2023-11-01 21:16:49 +0900 |
|---|---|---|
| committer | Leo Yu-Chi Liang | 2023-11-02 17:45:53 +0800 |
| commit | 88af85cf9266a0f29a610126f9c836ee7266c375 (patch) | |
| tree | 43dc772d22174d60cf2389fbea51087ffbb9313d /drivers/clk | |
| parent | 83b443df26c6f812e4cf053bad39d6dfe55342c2 (diff) | |
clk: starfive: jh7110: Add security clocks
Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
device.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/starfive/clk-jh7110.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 31aaf3340f9..a835541e48e 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -539,6 +539,16 @@ static int jh7110_stgcrg_init(struct udevice *dev) "pcie1_tl", "stg_axiahb", OFFSET(JH7110_STGCLK_PCIE1_TL))); + /* Security clocks */ + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK), + starfive_clk_gate(priv->reg, + "sec_ahb", "stg_axiahb", + OFFSET(JH7110_STGCLK_SEC_HCLK))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB), + starfive_clk_gate(priv->reg, + "sec_misc_ahb", "stg_axiahb", + OFFSET(JH7110_STGCLK_SEC_MISCAHB))); + return 0; } |