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authorTom Rini2021-09-30 11:29:41 -0400
committerTom Rini2021-09-30 11:29:41 -0400
commit8bef03683623d6a7adfff1f859ed44fad9e92ed7 (patch)
treebe2734e3581e083ce199230c259a192914651bff /drivers/clk
parentc8988efc884c680eb4f34295df6689a7e312c15d (diff)
parentdced079c53b283e15f04282f405de410a9be584d (diff)
Merge tag 'xilinx-for-v2022.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2022.01-rc1 zynq: - Enable capsule update for qspi and mmc - Update zed DT qspi compatible string zynqmp: - Add missing modeboot for EMMC - Add missing nand DT properties - List all eeproms for SC on vck190 - Add vck190 SC psu_init clk: - Handle only GATE type clock for Versal watchdog: - Update versal driver to handle system reset
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/clk_versal.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 62523d29099..a9dd57b098f 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk)
clk_id = priv->clk[clk->id].clk_id;
- return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+ if (versal_clock_gate(clk_id))
+ return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+
+ return 0;
}
static struct clk_ops versal_clk_ops = {