diff options
| author | Chin-Ting Kuo | 2022-08-19 17:01:02 +0800 |
|---|---|---|
| committer | Tom Rini | 2022-09-13 12:08:40 -0400 |
| commit | a7e82204743c3095deeac73e3142152d325141f8 (patch) | |
| tree | 9c0068279ccd7a5e1835d6fe184c9799b880c731 /drivers/clk | |
| parent | b3d9c0b6d5895e91b3e6b3566423d09e5a4d5ee8 (diff) | |
clk: aspeed: Get HCLK frequency support
User can get correct HCLK frequency during driver probe stage
by adding the following configuration in the device tree.
"clocks = <&scu ASPEED_CLK_AHB>".
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/aspeed/clk_ast2500.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index 623c6915b81..dc446ce9fb7 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -30,6 +30,12 @@ #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) +/* + * AXI/AHB clock selection, taken from Aspeed SDK + */ +#define SCU_HWSTRAP_AXIAHB_DIV_SHIFT 9 +#define SCU_HWSTRAP_AXIAHB_DIV_MASK (0x7 << SCU_HWSTRAP_AXIAHB_DIV_SHIFT) + DECLARE_GLOBAL_DATA_PTR; /* @@ -86,6 +92,20 @@ static ulong ast2500_get_clkin(struct ast2500_scu *scu) ? 25 * 1000 * 1000 : 24 * 1000 * 1000; } +static u32 ast2500_get_hclk(ulong clkin, struct ast2500_scu *scu) +{ + u32 hpll_reg = readl(&scu->h_pll_param); + ulong axi_div = 2; + u32 rate; + ulong ahb_div = 1 + ((readl(&scu->hwstrap) + & SCU_HWSTRAP_AXIAHB_DIV_MASK) + >> SCU_HWSTRAP_AXIAHB_DIV_SHIFT); + + rate = ast2500_get_hpll_rate(clkin, hpll_reg); + + return (rate / axi_div / ahb_div); +} + /** * Get current rate or uart clock * @@ -147,6 +167,9 @@ static ulong ast2500_clk_get_rate(struct clk *clk) rate = rate / apb_div; } break; + case ASPEED_CLK_AHB: + rate = ast2500_get_hclk(clkin, priv->scu); + break; case ASPEED_CLK_SDIO: { ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) |