diff options
| author | Dario Binacchi | 2023-11-11 11:46:18 +0100 |
|---|---|---|
| committer | Patrice Chotard | 2023-12-15 15:03:18 +0100 |
| commit | bd6eb5ddd715e7441d804c67f434418e172a1423 (patch) | |
| tree | 9878b23810c2287ba8f3578868f31c887c291de6 /drivers/clk | |
| parent | 555cf4c49594fba017b88e913bae1cb0992ea553 (diff) | |
clk: stm32f: fix setting of division factor for LCD_CLK
The value to be written to the register must be appropriately shifted,
as is correctly done in other parts of the code.
Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/stm32/clk-stm32f.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index ed7660196ef..4c186419335 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -530,7 +530,8 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate) /* set pll_saidivr with found value */ clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, - pllsaidivr_table[i]); + pllsaidivr_table[i] << + RCC_DCKCFGR_PLLSAIDIVR_SHIFT); return rate; } |