diff options
| author | Marek Vasut | 2023-09-17 16:11:30 +0200 |
|---|---|---|
| committer | Marek Vasut | 2023-10-01 00:08:28 +0200 |
| commit | e2c11b3c1872a204246165497cebc3b945e26dd8 (patch) | |
| tree | 4416ba75ba0efa20dba37b4ea26811fe8d498bf1 /drivers/clk | |
| parent | 0b93899bfb548a9590cc7723afb97a1f38f5232f (diff) | |
clk: renesas: Synchronize R8A77965 M3-N clock tables with Linux 6.5.3
Synchronize R-Car R8A77965 M3-N clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/renesas/r8a77965-cpg-mssr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 58e557a95f5..8a5c1525ece 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -50,7 +50,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a77965_core_clks[] = { +static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), @@ -124,7 +124,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] = { DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; -static const struct mssr_mod_clk r8a77965_mod_clks[] = { +static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1), DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6), DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2), @@ -302,7 +302,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = { (((md) & BIT(19)) >> 18) | \ (((md) & BIT(17)) >> 17)) -static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ { 1, 192, 1, 192, 1, 16, }, { 1, 192, 1, 128, 1, 16, }, |