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authorSam Protsenko2023-11-07 15:22:00 -0600
committerMinkyu Kang2023-11-13 16:39:05 +0900
commitf655090901dce2a3890efb07c3f341d5b8bc2ae9 (patch)
tree952bc8393318f73084071909cca265f0d5f4f602 /drivers/clk
parent2227f4c0afed9fef940ace67d1482417eb876316 (diff)
clk: exynos: Add header guard for clk-pll.h
The clk-pll.h is going to be included in multiple files soon. Add missing header guard to prevent possible build errors in future. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Fixes: 166097e87753 ("clk: exynos: add clock driver for Exynos7420 Soc") Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/exynos/clk-pll.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
index c79aac44258..7b7af5e6761 100644
--- a/drivers/clk/exynos/clk-pll.h
+++ b/drivers/clk/exynos/clk-pll.h
@@ -5,4 +5,9 @@
* Thomas Abraham <thomas.ab@samsung.com>
*/
+#ifndef __EXYNOS_CLK_PLL_H
+#define __EXYNOS_CLK_PLL_H
+
unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
+
+#endif /* __EXYNOS_CLK_PLL_H */