diff options
| author | Saksham Jain | 2016-03-23 16:24:42 +0530 |
|---|---|---|
| committer | York Sun | 2016-03-29 08:46:22 -0700 |
| commit | 8a6f83dcb8638e34c264e6ee8ee5699975de68a0 (patch) | |
| tree | d1a45ee6ae8360286e17e02b0a8b0e30408beb5f /drivers/crypto/fsl/jr.h | |
| parent | 69b6a796f7a7cf2a7946e07e32346bf5595829d5 (diff) | |
crypto/fsl: Make CAAM transactions cacheable
This commit solves CAAM coherency issue on ls2080. When caches are
enabled and CAAM's DMA's AXI transcations are not made cacheable,
Core reads/writes data from/to caches and CAAM does from main memory.
This forces data flushes to synchronize various data structures. But
even if any data in proximity of these structures is read by core,
these structures again are fetched in caches.
To avoid this problem, either all the data that CAAM accesses can be
made cache line aligned or CAAM transcations can be made cacheable.
So, this commit makes CAAM transcations as write back with write and
read allocate.
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'drivers/crypto/fsl/jr.h')
| -rw-r--r-- | drivers/crypto/fsl/jr.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 545d964cedd..1642dbbf4c2 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -23,6 +23,9 @@ #define MCFGR_PS_SHIFT 16 #define MCFGR_AWCACHE_SHIFT 8 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) +#define MCFGR_ARCACHE_SHIFT 12 +#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) + #define JR_INTMASK 0x00000001 #define JRCR_RESET 0x01 #define JRINT_ERR_HALT_INPROGRESS 0x4 |