diff options
| author | Bai Ping | 2019-08-08 09:59:05 +0000 |
|---|---|---|
| committer | Stefano Babic | 2019-10-08 16:36:37 +0200 |
| commit | 7b14cc991ba85d2b035479177cc1391ed729abd3 (patch) | |
| tree | 4cdfbc1d24d7e338454ced1b2283a947b6f7b25e /drivers/ddr/imx | |
| parent | ca729cd16cca26a8d8a1746e3080937206aca615 (diff) | |
imx8mq: Update the ddrc QoS setting for B1 chip
Update the ddrc Qos setting for B1 to align with B0's setting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Robby Cai <robby.cai@nxp.com>
Diffstat (limited to 'drivers/ddr/imx')
| -rw-r--r-- | drivers/ddr/imx/imx8m/lpddr4_init.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/ddr/imx/imx8m/lpddr4_init.c b/drivers/ddr/imx/imx8m/lpddr4_init.c index a4bc1de8eb6..0f46ca02b6c 100644 --- a/drivers/ddr/imx/imx8m/lpddr4_init.c +++ b/drivers/ddr/imx/imx8m/lpddr4_init.c @@ -54,7 +54,10 @@ void ddr_init(struct dram_timing_info *dram_timing) reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ debug("DDRINFO: cfg clk\n"); - dram_pll_init(MHZ(750)); + if (is_imx8mq()) + dram_pll_init(MHZ(800)); + else + dram_pll_init(MHZ(750)); /* * release [0]ddr1_preset_n, [1]ddr1_core_reset_n, |