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authorPeng Fan2019-08-27 06:24:47 +0000
committerStefano Babic2019-10-08 16:36:36 +0200
commit28cb058ff748aa592014fcc8049b6bac1e2e4a2e (patch)
tree6c125d3e19cd179487f1784812ea8e097cd4c6f2 /drivers/ddr
parent4b78bb504142ebc97efae6908e666cb0608ebf86 (diff)
ddr: imx8m: fix ddr firmware location when enable SPL OF
With CONFIG_SPL_OF_CONTROL, the device tree will be padded to end of the u-boot-spl-nodtb.bin, however we also put the ddr firmware file to this location, so need to adapt the code with SPL OF and align to 4 bytes to ease copy firmware. Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/ddr')
-rw-r--r--drivers/ddr/imx/imx8m/helper.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c
index 61cd4f6db12..3e605353ea1 100644
--- a/drivers/ddr/imx/imx8m/helper.c
+++ b/drivers/ddr/imx/imx8m/helper.c
@@ -31,7 +31,17 @@ void ddr_load_train_firmware(enum fw_type type)
unsigned long pr_to32, pr_from32;
unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
unsigned long imem_start = (unsigned long)&_end + fw_offset;
- unsigned long dmem_start = imem_start + IMEM_LEN;
+ unsigned long dmem_start;
+
+#ifdef CONFIG_SPL_OF_CONTROL
+ if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
+ imem_start = roundup((unsigned long)&_end +
+ fdt_totalsize(gd->fdt_blob), 4) +
+ fw_offset;
+ }
+#endif
+
+ dmem_start = imem_start + IMEM_LEN;
pr_from32 = imem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;