global: Move remaining CONFIG_SYS_* to CFG_SYS_*

The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

6 files changed, 43 insertions, 43 deletions

diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c
index a1ff47035be..ca49ee40a71 100644
--- a/drivers/fpga/ACEX1K.c
+++ b/drivers/fpga/ACEX1K.c
@@ -24,8 +24,8 @@
 #define CONFIG_FPGA_DELAY()
 #endif
 
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10		/* 100 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10		/* 100 ms */
 #endif
 
 static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
@@ -138,7 +138,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 		ts = get_timer (0);		/* get current time */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for STATUS to go high.\n");
 				(*fn->abort) (cookie);
 				return FPGA_FAIL;
diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c
index f264ff8c0ec..3eed461e1e5 100644
--- a/drivers/fpga/cyclon2.c
+++ b/drivers/fpga/cyclon2.c
@@ -22,8 +22,8 @@
 #define CONFIG_FPGA_DELAY()
 #endif
 
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10		/* 100 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10		/* 100 ms */
 #endif
 
 static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
@@ -130,7 +130,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 		ts = get_timer(0);		/* get current time */
 		do {
 			CONFIG_FPGA_DELAY();
-			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+			if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
 				/* check the time */
 				puts("** Timeout waiting for STATUS to go high.\n");
 				(*fn->abort) (cookie);
diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index f72dfdec94e..57a4532f736 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -21,8 +21,8 @@
 #define CONFIG_FPGA_DELAY()
 #endif
 
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
 #endif
 
 static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
@@ -149,7 +149,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		/* Now wait for INIT and BUSY to go high */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to clear.\n");
 				(*fn->abort) (cookie);	/* abort the burn */
 				return FPGA_FAIL;
@@ -182,7 +182,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				CONFIG_FPGA_DELAY ();
 				(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
-				if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+				if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 					puts ("** Timeout waiting for BUSY to clear.\n");
 					(*fn->abort) (cookie);	/* abort the burn */
 					return FPGA_FAIL;
@@ -214,7 +214,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 			CONFIG_FPGA_DELAY ();
 			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for DONE to clear.\n");
 				(*fn->abort) (cookie);	/* abort the burn */
 				ret_val = FPGA_FAIL;
@@ -333,7 +333,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		ts = get_timer (0);		/* get current time */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to start.\n");
 				return FPGA_FAIL;
 			}
@@ -347,7 +347,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		/* Now wait for INIT to go high */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to clear.\n");
 				return FPGA_FAIL;
 			}
@@ -404,7 +404,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 
 			putc ('*');
 
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for DONE to clear.\n");
 				ret_val = FPGA_FAIL;
 				break;
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index b7a063a95fc..fdec89bb815 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -26,8 +26,8 @@
 #define CONFIG_FPGA_DELAY()
 #endif
 
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
 #endif
 
 static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
@@ -154,7 +154,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		/* Now wait for INIT and BUSY to go high */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to clear.\n");
 				(*fn->abort) (cookie);	/* abort the burn */
 				return FPGA_FAIL;
@@ -187,7 +187,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				CONFIG_FPGA_DELAY ();
 				(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
-				if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+				if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 					puts ("** Timeout waiting for BUSY to clear.\n");
 					(*fn->abort) (cookie);	/* abort the burn */
 					return FPGA_FAIL;
@@ -221,7 +221,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 			CONFIG_FPGA_DELAY ();
 			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for DONE to clear.\n");
 				(*fn->abort) (cookie);	/* abort the burn */
 				ret_val = FPGA_FAIL;
@@ -340,7 +340,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		ts = get_timer (0);		/* get current time */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to start.\n");
 				if (*fn->abort)
 					(*fn->abort) (cookie);
@@ -356,7 +356,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		/* Now wait for INIT to go high */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to clear.\n");
 				if (*fn->abort)
 					(*fn->abort) (cookie);
@@ -423,7 +423,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 
 			putc ('*');
 
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for DONE to clear.\n");
 				ret_val = FPGA_FAIL;
 				break;
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index 0d536f0d044..8871deaea6f 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -49,8 +49,8 @@
  * which yields 11.44 mS.  So let's make it bigger in order to handle
  * an XC2V1000, if anyone can ever get ahold of one.
  */
-#ifndef CONFIG_SYS_FPGA_WAIT_INIT
-#define CONFIG_SYS_FPGA_WAIT_INIT	CONFIG_SYS_HZ / 2	/* 500 ms */
+#ifndef CFG_SYS_FPGA_WAIT_INIT
+#define CFG_SYS_FPGA_WAIT_INIT	CONFIG_SYS_HZ / 2	/* 500 ms */
 #endif
 
 /*
@@ -58,15 +58,15 @@
  * This is normally not necessary since for most reasonable configuration
  * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
  */
-#ifndef CONFIG_SYS_FPGA_WAIT_BUSY
-#define CONFIG_SYS_FPGA_WAIT_BUSY	CONFIG_SYS_HZ / 200	/* 5 ms*/
+#ifndef CFG_SYS_FPGA_WAIT_BUSY
+#define CFG_SYS_FPGA_WAIT_BUSY	CONFIG_SYS_HZ / 200	/* 5 ms*/
 #endif
 
 /* Default timeout for waiting for FPGA to enter operational mode after
  * configuration data has been written.
  */
-#ifndef	CONFIG_SYS_FPGA_WAIT_CONFIG
-#define CONFIG_SYS_FPGA_WAIT_CONFIG	CONFIG_SYS_HZ / 5	/* 200 ms */
+#ifndef	CFG_SYS_FPGA_WAIT_CONFIG
+#define CFG_SYS_FPGA_WAIT_CONFIG	CONFIG_SYS_HZ / 5	/* 200 ms */
 #endif
 
 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
@@ -190,9 +190,9 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
 	udelay(10);
 	ts = get_timer(0);
 	do {
-		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+		if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
 			printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
-			       __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+			       __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
 			(*fn->abort)(cookie);
 			return FPGA_FAIL;
 		}
@@ -209,9 +209,9 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
 	ts = get_timer(0);
 	do {
 		CONFIG_FPGA_DELAY();
-		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+		if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
 			printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
-			       __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+			       __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
 			(*fn->abort)(cookie);
 			return FPGA_FAIL;
 		}
@@ -260,9 +260,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
 				break;
 		}
 
-		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
+		if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) {
 			printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
-			       __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
+			       __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG);
 			(*fn->abort)(cookie);
 			ret_val = FPGA_FAIL;
 			break;
@@ -350,10 +350,10 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
 		ts = get_timer(0);
 		while ((*fn->busy)(cookie)) {
-			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
+			if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) {
 				printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
 				       __func__, __LINE__,
-				       CONFIG_SYS_FPGA_WAIT_BUSY);
+				       CFG_SYS_FPGA_WAIT_BUSY);
 				(*fn->abort)(cookie);
 				return FPGA_FAIL;
 			}
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 0c83df46da4..53dd780a6ca 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -36,8 +36,8 @@
 #define DEVCFG_MCTRL_RFIFO_FLUSH	0x00000002
 #define DEVCFG_MCTRL_WFIFO_FLUSH	0x00000001
 
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
 #endif
 
 #ifndef CONFIG_SYS_FPGA_PROG_TIME
@@ -232,7 +232,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype)
 		/* Polling the PCAP_INIT status for Reset */
 		ts = get_timer(0);
 		while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
-			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+			if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
 				printf("%s: Timeout wait for INIT to clear\n",
 				       __func__);
 				return FPGA_FAIL;
@@ -246,7 +246,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype)
 		ts = get_timer(0);
 		while (!(readl(&devcfg_base->status) &
 			DEVCFG_STATUS_PCFG_INIT)) {
-			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+			if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
 				printf("%s: Timeout wait for INIT to set\n",
 				       __func__);
 				return FPGA_FAIL;
@@ -400,7 +400,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
 	/* Check FPGA configuration completion */
 	ts = get_timer(0);
 	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
-		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+		if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
 			printf("%s: Timeout wait for FPGA to config\n",
 			       __func__);
 			return FPGA_FAIL;
@@ -484,7 +484,7 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
 	/* Check FPGA configuration completion */
 	ts = get_timer(0);
 	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
-		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+		if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
 			printf("%s: Timeout wait for FPGA to config\n",
 			       __func__);
 			return FPGA_FAIL;
@@ -561,7 +561,7 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
 		/* Check FPGA configuration completion */
 		ts = get_timer(0);
 		while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
-			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+			if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
 				printf("%s: Timeout wait for FPGA to config\n",
 				       __func__);
 				return FPGA_FAIL;