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authorTom Rini2023-01-10 11:19:45 -0500
committerTom Rini2023-01-20 12:27:24 -0500
commit6e7df1d151a7a127caf3b62ff6dfc003fc2aefcd (patch)
treeae38e9dcf468b2e4e58293561fae87895d9b549f /drivers/fpga
parentad242344681f6a0076a6bf100aa83ac9ecbea355 (diff)
global: Finish CONFIG -> CFG migration
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/fpga')
-rw-r--r--drivers/fpga/virtex2.c8
-rw-r--r--drivers/fpga/zynqpl.c6
2 files changed, 7 insertions, 7 deletions
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index fc99a5f4831..3ded27f9b3f 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -34,8 +34,8 @@
/*
* Check for errors during configuration by default
*/
-#ifndef CONFIG_SYS_FPGA_CHECK_ERROR
-#define CONFIG_SYS_FPGA_CHECK_ERROR
+#ifndef CFG_SYS_FPGA_CHECK_ERROR
+#define CFG_SYS_FPGA_CHECK_ERROR
#endif
/*
@@ -323,7 +323,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
break;
}
-#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
+#ifdef CFG_SYS_FPGA_CHECK_ERROR
if ((*fn->init)(cookie)) {
printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
__func__, __LINE__);
@@ -458,7 +458,7 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
break;
}
-#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
+#ifdef CFG_SYS_FPGA_CHECK_ERROR
if ((*fn->init)(cookie)) {
printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
__func__, __LINE__);
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 53dd780a6ca..a2e3b305fa4 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -40,8 +40,8 @@
#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-#ifndef CONFIG_SYS_FPGA_PROG_TIME
-#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
+#ifndef CFG_SYS_FPGA_PROG_TIME
+#define CFG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
#endif
#define DUMMY_WORD 0xffffffff
@@ -181,7 +181,7 @@ static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
return FPGA_FAIL;
}
- if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
+ if (get_timer(ts) > CFG_SYS_FPGA_PROG_TIME) {
printf("%s: Timeout wait for DMA to complete\n",
__func__);
return FPGA_FAIL;