diff options
| author | Simon Glass | 2016-11-23 06:34:43 -0700 |
|---|---|---|
| committer | Heiko Schocher | 2016-12-05 13:27:54 +0100 |
| commit | 37b8eb37f8950538425d9956b65e8911a986002b (patch) | |
| tree | a67f6cc0dc7e3b864f7a0659ba5aa1f69212e221 /drivers/i2c/s3c24x0_i2c.h | |
| parent | 9a1bff69cdff6e825290dff94cc912b58120669f (diff) | |
samsung: i2c: Split the high-speed I2C code into a new driver
Now that driver model is used for I2C on all boards, we can split the
high-speed code into its own driver. There is virtually no common code,
and this significantly reduces confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'drivers/i2c/s3c24x0_i2c.h')
| -rw-r--r-- | drivers/i2c/s3c24x0_i2c.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h index 1ae73d27777..aa10fc73cd7 100644 --- a/drivers/i2c/s3c24x0_i2c.h +++ b/drivers/i2c/s3c24x0_i2c.h @@ -59,4 +59,26 @@ struct s3c24x0_i2c_bus { unsigned clk_cycle; unsigned clk_div; }; + +#define I2C_WRITE 0 +#define I2C_READ 1 + +#define I2C_OK 0 +#define I2C_NOK 1 +#define I2C_NACK 2 +#define I2C_NOK_LA 3 /* Lost arbitration */ +#define I2C_NOK_TOUT 4 /* time out */ + +/* S3C I2C Controller bits */ +#define I2CSTAT_BSY 0x20 /* Busy bit */ +#define I2CSTAT_NACK 0x01 /* Nack bit */ +#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ +#define I2CCON_IRPND 0x10 /* Interrupt pending bit */ +#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ +#define I2C_MODE_MR 0x80 /* Master Receive Mode */ +#define I2C_START_STOP 0x20 /* START / STOP */ +#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ + +#define I2C_TIMEOUT_MS 10 /* 10 ms */ + #endif /* _S3C24X0_I2C_H */ |