diff options
| author | Ye Li | 2023-06-15 18:09:12 +0800 |
|---|---|---|
| committer | Stefano Babic | 2023-07-13 11:29:40 +0200 |
| commit | 71a21425d278a07ba263109fff0cba09ff30a157 (patch) | |
| tree | 0fbf9fc35fa985ccf06a8dbb04b132e37318f8dd /drivers/misc/imx_ele | |
| parent | 859f4e02a8fa9be522a5aefcc56a5dd8f702e5be (diff) | |
imx: misc: ele_mu: Update MU TR registers count
According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All
of them are used for ELE message. So update TR count to 8 and fix a
typo in receive msg
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/misc/imx_ele')
| -rw-r--r-- | drivers/misc/imx_ele/ele_mu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index 0d34b8c9010..956f8a1eb2f 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -22,7 +22,7 @@ struct imx8ulp_mu { #define MU_SR_TE0_MASK BIT(0) #define MU_SR_RF0_MASK BIT(0) -#define MU_TR_COUNT 4 +#define MU_TR_COUNT 8 #define MU_RR_COUNT 4 void mu_hal_init(ulong base) @@ -65,7 +65,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) u32 val; int ret; - assert(reg_index < MU_TR_COUNT); + assert(reg_index < MU_RR_COUNT); debug("receivemsg sr 0x%x\n", readl(&mu_base->sr)); |