Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86

- New timer API to allow delays with a 32-bit microsecond timer
- Add dynamic ACPI structs (DSDT/SSDT) generations to the DM core
- x86: Enable ACPI table generation by default
- x86: Enable the copy framebuffer on Coral
- x86: A few fixes to FSP2 with ApolloLake
- x86: Drop setup_pcat_compatibility()
- x86: Primary-to-Sideband Bus minor fixes

4 files changed, 57 insertions, 17 deletions

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 6bb5bc77e9f..b67e906a76b 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -243,10 +243,10 @@ config NUVOTON_NCT6102D
 	  in the Nuvoton Super IO chips on X86 platforms.
 
 config P2SB
-	bool "Intel Primary-to-Sideband Bus"
+	bool "Intel Primary to Sideband Bridge"
 	depends on X86 || SANDBOX
 	help
-	  This enables support for the Intel Primary-to-Sideband bus,
+	  This enables support for the Intel Primary to Sideband Bridge,
 	  abbreviated to P2SB. The P2SB is used to access various peripherals
 	  such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
 	  space. The space is segmented into different channels and peripherals
@@ -256,20 +256,20 @@ config P2SB
 	  devices - see pcr_readl(), etc.
 
 config SPL_P2SB
-	bool "Intel Primary-to-Sideband Bus in SPL"
+	bool "Intel Primary to Sideband Bridge in SPL"
 	depends on SPL && (X86 || SANDBOX)
 	help
-	  The Primary-to-Sideband bus is used to access various peripherals
+	  The Primary to Sideband Bridge is used to access various peripherals
 	  through memory-mapped I/O in a large chunk of PCI space. The space is
 	  segmented into different channels and peripherals are accessed by
 	  device-specific means within those channels. Devices should be added
 	  in the device tree as subnodes of the p2sb.
 
 config TPL_P2SB
-	bool "Intel Primary-to-Sideband Bus in TPL"
+	bool "Intel Primary to Sideband Bridge in TPL"
 	depends on TPL && (X86 || SANDBOX)
 	help
-	  The Primary-to-Sideband bus is used to access various peripherals
+	  The Primary to Sideband Bridge is used to access various peripherals
 	  through memory-mapped I/O in a large chunk of PCI space. The space is
 	  segmented into different channels and peripherals are accessed by
 	  device-specific means within those channels. Devices should be added
diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c
index ec70866cc3e..94fa233f193 100644
--- a/drivers/misc/irq-uclass.c
+++ b/drivers/misc/irq-uclass.c
@@ -152,8 +152,6 @@ int irq_request(struct udevice *dev, struct irq *irq)
 	const struct irq_ops *ops;
 
 	log_debug("(dev=%p, irq=%p)\n", dev, irq);
-	if (!irq)
-		return 0;
 	ops = irq_get_ops(dev);
 
 	irq->dev = dev;
@@ -170,11 +168,27 @@ int irq_first_device_type(enum irq_dev_t type, struct udevice **devp)
 
 	ret = uclass_first_device_drvdata(UCLASS_IRQ, type, devp);
 	if (ret)
-		return log_msg_ret("find", ret);
+		return ret;
 
 	return 0;
 }
 
+#if CONFIG_IS_ENABLED(ACPIGEN)
+int irq_get_acpi(const struct irq *irq, struct acpi_irq *acpi_irq)
+{
+	struct irq_ops *ops;
+
+	if (!irq_is_valid(irq))
+		return -EINVAL;
+
+	ops = irq_get_ops(irq->dev);
+	if (!ops->get_acpi)
+		return -ENOSYS;
+
+	return ops->get_acpi(irq, acpi_irq);
+}
+#endif
+
 UCLASS_DRIVER(irq) = {
 	.id		= UCLASS_IRQ,
 	.name		= "irq",
diff --git a/drivers/misc/irq_sandbox.c b/drivers/misc/irq_sandbox.c
index 54bc47c8d8a..a2511b32fcd 100644
--- a/drivers/misc/irq_sandbox.c
+++ b/drivers/misc/irq_sandbox.c
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <dm.h>
 #include <irq.h>
+#include <acpi/acpi_device.h>
 #include <asm/test.h>
 
 /**
@@ -73,6 +74,18 @@ static int sandbox_irq_of_xlate(struct irq *irq,
 	return 0;
 }
 
+static __maybe_unused int sandbox_get_acpi(const struct irq *irq,
+					   struct acpi_irq *acpi_irq)
+{
+	acpi_irq->pin = irq->id;
+	acpi_irq->mode = ACPI_IRQ_LEVEL_TRIGGERED;
+	acpi_irq->polarity = ACPI_IRQ_ACTIVE_HIGH;
+	acpi_irq->shared = ACPI_IRQ_SHARED;
+	acpi_irq->wake = ACPI_IRQ_WAKE;
+
+	return 0;
+}
+
 static const struct irq_ops sandbox_irq_ops = {
 	.route_pmc_gpio_gpe	= sandbox_route_pmc_gpio_gpe,
 	.set_polarity		= sandbox_set_polarity,
@@ -80,6 +93,9 @@ static const struct irq_ops sandbox_irq_ops = {
 	.restore_polarities	= sandbox_restore_polarities,
 	.read_and_clear		= sandbox_irq_read_and_clear,
 	.of_xlate		= sandbox_irq_of_xlate,
+#if CONFIG_IS_ENABLED(ACPIGEN)
+	.get_acpi		= sandbox_get_acpi,
+#endif
 };
 
 static const struct udevice_id sandbox_irq_ids[] = {
diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c
index 06b1e8d9ad7..b5219df46be 100644
--- a/drivers/misc/p2sb-uclass.c
+++ b/drivers/misc/p2sb-uclass.c
@@ -18,7 +18,17 @@
 
 #define PCR_COMMON_IOSF_1_0	1
 
-static void *_pcr_reg_address(struct udevice *dev, uint offset)
+int p2sb_set_hide(struct udevice *dev, bool hide)
+{
+	struct p2sb_ops *ops = p2sb_get_ops(dev);
+
+	if (!ops->set_hide)
+		return -ENOSYS;
+
+	return ops->set_hide(dev, hide);
+}
+
+void *pcr_reg_address(struct udevice *dev, uint offset)
 {
 	struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
 	struct udevice *p2sb = dev_get_parent(dev);
@@ -55,7 +65,7 @@ uint pcr_read32(struct udevice *dev, uint offset)
 	/* Ensure the PCR offset is correctly aligned */
 	assert(IS_ALIGNED(offset, sizeof(uint32_t)));
 
-	ptr = _pcr_reg_address(dev, offset);
+	ptr = pcr_reg_address(dev, offset);
 	val = readl(ptr);
 	unmap_sysmem(ptr);
 
@@ -67,7 +77,7 @@ uint pcr_read16(struct udevice *dev, uint offset)
 	/* Ensure the PCR offset is correctly aligned */
 	check_pcr_offset_align(offset, sizeof(uint16_t));
 
-	return readw(_pcr_reg_address(dev, offset));
+	return readw(pcr_reg_address(dev, offset));
 }
 
 uint pcr_read8(struct udevice *dev, uint offset)
@@ -75,7 +85,7 @@ uint pcr_read8(struct udevice *dev, uint offset)
 	/* Ensure the PCR offset is correctly aligned */
 	check_pcr_offset_align(offset, sizeof(uint8_t));
 
-	return readb(_pcr_reg_address(dev, offset));
+	return readb(pcr_reg_address(dev, offset));
 }
 
 /*
@@ -86,7 +96,7 @@ uint pcr_read8(struct udevice *dev, uint offset)
  */
 static void write_completion(struct udevice *dev, uint offset)
 {
-	readl(_pcr_reg_address(dev, ALIGN_DOWN(offset, sizeof(uint32_t))));
+	readl(pcr_reg_address(dev, ALIGN_DOWN(offset, sizeof(uint32_t))));
 }
 
 void pcr_write32(struct udevice *dev, uint offset, uint indata)
@@ -94,7 +104,7 @@ void pcr_write32(struct udevice *dev, uint offset, uint indata)
 	/* Ensure the PCR offset is correctly aligned */
 	assert(IS_ALIGNED(offset, sizeof(indata)));
 
-	writel(indata, _pcr_reg_address(dev, offset));
+	writel(indata, pcr_reg_address(dev, offset));
 	/* Ensure the writes complete */
 	write_completion(dev, offset);
 }
@@ -104,7 +114,7 @@ void pcr_write16(struct udevice *dev, uint offset, uint indata)
 	/* Ensure the PCR offset is correctly aligned */
 	check_pcr_offset_align(offset, sizeof(uint16_t));
 
-	writew(indata, _pcr_reg_address(dev, offset));
+	writew(indata, pcr_reg_address(dev, offset));
 	/* Ensure the writes complete */
 	write_completion(dev, offset);
 }
@@ -114,7 +124,7 @@ void pcr_write8(struct udevice *dev, uint offset, uint indata)
 	/* Ensure the PCR offset is correctly aligned */
 	check_pcr_offset_align(offset, sizeof(uint8_t));
 
-	writeb(indata, _pcr_reg_address(dev, offset));
+	writeb(indata, pcr_reg_address(dev, offset));
 	/* Ensure the writes complete */
 	write_completion(dev, offset);
 }