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authorMarek Vasut2018-06-13 08:02:55 +0200
committerMarek Vasut2018-12-03 12:51:16 +0100
commit8ec6a04b6bf641f13402506c0f1b1d9dda699b51 (patch)
tree260d487305cc56e7fda179b37f5b4ccfaaef020c /drivers/mmc/tmio-common.h
parenteb2acbafff06fa116074f80b06e47b605cd2fef2 (diff)
mmc: tmio: Switch to clock framework
Switch the driver to using clk_get_rate()/clk_set_rate() instead of caching the mclk frequency in it's private data. This is required on the SDHI variant of the controller, where the upstream mclk need to be adjusted when using UHS modes. Platforms which do not support clock framework or do not support it in eg. SPL default to 100 MHz clock. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> --- V2: - Fix build on certain platforms using SPL without clock framework V3: - Turn clk_get_rate into a callback and fill it as needed on both renesas and socionext platforms
Diffstat (limited to 'drivers/mmc/tmio-common.h')
-rw-r--r--drivers/mmc/tmio-common.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h
index 792b1ba5ae6..6591c61c3c4 100644
--- a/drivers/mmc/tmio-common.h
+++ b/drivers/mmc/tmio-common.h
@@ -117,7 +117,6 @@ struct tmio_sd_plat {
struct tmio_sd_priv {
void __iomem *regbase;
- unsigned long mclk;
unsigned int version;
u32 caps;
#define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
@@ -133,6 +132,10 @@ struct tmio_sd_priv {
#ifdef CONFIG_DM_REGULATOR
struct udevice *vqmmc_dev;
#endif
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+#endif
+ ulong (*clk_get_rate)(struct tmio_sd_priv *);
};
int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,