diff options
| author | Vasily Khoruzhick | 2023-03-07 13:26:46 -0800 |
|---|---|---|
| committer | Kever Yang | 2023-04-21 15:16:00 +0800 |
| commit | 7786710adb76720be8e693c4efcea039af7ae086 (patch) | |
| tree | 6a9a5c48e768cbd859ee9e30d672cc851865db21 /drivers/mmc | |
| parent | 5db4972a5bbdbf9e3af48ffc9bc4fec73b7b6a79 (diff) | |
rockchip: sdhci: rk3568: fix clock setting logic
mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post
uses it if its != 0, regardless of mmc->clock value, and it breaks
eMMC controller.
Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for
breaking eMMC, since first initialization sets mmc->mmc_tran speed
to non-zero value (26MHz in my case), and on subsequent re-init when
mmc layer asks for 400KHz it sets 26MHz instead.
Fix it by using MAX(mmc->tran_speed, mmc->clock)
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/rockchip_sdhci.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index e1409dd2c74..fef23f593e8 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -401,11 +401,11 @@ static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host) static int rk3568_sdhci_set_ios_post(struct sdhci_host *host) { struct mmc *mmc = host->mmc; - uint clock = mmc->tran_speed; + uint clock = mmc->clock; u32 reg, vendor_reg; - if (!clock) - clock = mmc->clock; + if (mmc->tran_speed && mmc->clock > mmc->tran_speed) + clock = mmc->tran_speed; rk3568_sdhci_emmc_set_clock(host, clock); |