diff options
| author | Peng Fan | 2018-01-02 16:51:22 +0800 |
|---|---|---|
| committer | Jaehoon Chung | 2018-01-13 00:08:44 +0900 |
| commit | db359efd5907edbeaea2e3eb3504729f60208cd8 (patch) | |
| tree | 24ed846db8b25f6fadb589f134304f3edbcf4598 /drivers/mmc | |
| parent | 8c0bb8582459a739ac27eda3d738734e489d0465 (diff) | |
mmc: fsl_esdhc: Fix eMMC 1.8v setting issue
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.
Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index cca57f8a79d..71c62f42337 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -647,7 +647,11 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) esdhc_write32(®s->clktunectrlstatus, 0x0); /* Put VEND_SPEC to default value */ - esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); + if (priv->vs18_enable) + esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT | + ESDHC_VENDORSPEC_VSELECT)); + else + esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); /* Disable DLL_CTRL delay line */ esdhc_write32(®s->dllctrl, 0x0); @@ -676,9 +680,6 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) /* Set timout to the maximum value */ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); - if (priv->vs18_enable) - esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); - return 0; } |