diff options
| author | Marek Vasut | 2018-05-24 21:58:45 +0200 |
|---|---|---|
| committer | Jagan Teki | 2018-06-28 19:58:40 +0530 |
| commit | 069b746ad9e66ab75973020f992e059c06cf3a7c (patch) | |
| tree | ccb99901b454aad9a7f99761ebc921b2dcbb9156 /drivers/mtd/spi | |
| parent | c0eaffa03959a97e6c139ea023e4041170e105e6 (diff) | |
sf: Enable FSR polling on N25Q256(A)
The N25Q256(A) datasheet clearly states that this device does have
a Flag Status Register and does update FSR PEC bit 7 during Program
and Erase cycles to indicate the cycle is in progress. Enable the
FSR PEC bit polling on this device to prevent data corruption.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/mtd/spi')
| -rw-r--r-- | drivers/mtd/spi/spi_flash_ids.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index 54d491c8734..9212373daec 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -134,8 +134,8 @@ const struct spi_flash_info spi_flash_ids[] = { {"n25q64a", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, {"n25q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, {"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, - {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"n25q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"n25q512a", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"n25q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, |