diff options
| author | Alex Marginean | 2019-07-15 11:48:47 +0300 |
|---|---|---|
| committer | Joe Hershberger | 2019-07-25 13:13:30 -0500 |
| commit | 9bc07e8174bf29432c43c8e1ffa87e3730120112 (patch) | |
| tree | 8edcb1a23706984fb439324c7b81690b85ec4d09 /drivers/net/fsl_enetc.h | |
| parent | 9b844314fd75d9c24708c7e477d5ce3273f13048 (diff) | |
drivers: net: fsl_enetc: add support for SGMII 2500
SGMII 2500 as supported on NXP SoCs requires AN to be disabled, handle
this case in the enetc sgmii init code.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers/net/fsl_enetc.h')
| -rw-r--r-- | drivers/net/fsl_enetc.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h index 7ac7c1fefea..0bb4cdff479 100644 --- a/drivers/net/fsl_enetc.h +++ b/drivers/net/fsl_enetc.h @@ -183,7 +183,7 @@ struct enetc_priv { #define ENETC_PCS_CR 0x00 #define ENETC_PCS_CR_RESET_AN 0x1200 #define ENETC_PCS_CR_DEF_VAL 0x0140 -#define ENETC_PCS_CR_LANE_RESET 0x8000 +#define ENETC_PCS_CR_RST BIT(15) #define ENETC_PCS_DEV_ABILITY 0x04 #define ENETC_PCS_DEV_ABILITY_SGMII 0x4001 #define ENETC_PCS_DEV_ABILITY_SXGMII 0x5001 @@ -192,7 +192,9 @@ struct enetc_priv { #define ENETC_PCS_LINK_TIMER2 0x13 #define ENETC_PCS_LINK_TIMER2_VAL 0x0003 #define ENETC_PCS_IF_MODE 0x14 -#define ENETC_PCS_IF_MODE_SGMII_AN 0x0003 +#define ENETC_PCS_IF_MODE_SGMII BIT(0) +#define ENETC_PCS_IF_MODE_SGMII_AN BIT(1) +#define ENETC_PCS_IF_MODE_SPEED_1G BIT(3) /* PCS replicator block for USXGMII */ #define ENETC_PCS_DEVAD_REPL 0x1f |