diff options
| author | Peter Chubb | 2016-09-14 01:29:03 +0000 |
|---|---|---|
| committer | Joe Hershberger | 2016-10-13 12:25:29 -0500 |
| commit | 7377647a3678c50c1913f05d8ad8d685b05e52d1 (patch) | |
| tree | 3505578bf558c212ac7a96a61079ac612b5a657b /drivers/net/rtl8169.c | |
| parent | c86ff7fdb2272e25c8abba2e36d4f28f9282cd37 (diff) | |
rtl8169: fix cache misalignment message on transmit.
The call to flush cache on the transmit buffer was misplaced (for very
short packets) and asked to flush less than a cacheline.
Move the flush cache call to after a short packet has been padded
to minimum length (so the padding is flushed too), and round the size
up to a cacheline.
Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers/net/rtl8169.c')
| -rw-r--r-- | drivers/net/rtl8169.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 1cc0b40935c..a3f4423a20c 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -629,11 +629,12 @@ static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase, /* point to the current txb incase multiple tx_rings are used */ ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; memcpy(ptxb, (char *)packet, (int)length); - rtl_flush_buffer(ptxb, length); while (len < ETH_ZLEN) ptxb[len++] = '\0'; + rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN)); + tpc->TxDescArray[entry].buf_Haddr = 0; #ifdef CONFIG_DM_ETH tpc->TxDescArray[entry].buf_addr = cpu_to_le32( |