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authorWasim Khan2020-01-06 12:05:57 +0000
committerPriyanka Jain2020-01-24 14:28:26 +0530
commit1185b229cca55a5ce3ee7bb35b203f788254f1a1 (patch)
tree8792b9b256eb80f81cb4ac34447d3716ddc56ccb /drivers/pci/pcie_layerscape_fixup_common.c
parentd085c9ad06e9c98a94985772685ea1df6befed99 (diff)
pci: layerscape: Common device tree fixup for NXP SoCs
Add Common device tree fixup for NXP SoCs. Based on SoC and revision call pcie_layerscape or pcie_layerscape_gen4 fixup. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'drivers/pci/pcie_layerscape_fixup_common.c')
-rw-r--r--drivers/pci/pcie_layerscape_fixup_common.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c
new file mode 100644
index 00000000000..b32236e5f85
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2020 NXP
+ *
+ * PCIe DT fixup for NXP Layerscape SoCs
+ * Author: Wasim Khan <wasim.khan@nxp.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/soc.h>
+#include "pcie_layerscape_fixup_common.h"
+
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+#if defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
+ uint svr;
+
+ svr = SVR_SOC_VER(get_svr());
+
+ if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 1, 0))
+ ft_pci_setup_ls_gen4(blob, bd);
+ else
+#endif /* CONFIG_PCIE_LAYERSCAPE_GEN4 */
+ ft_pci_setup_ls(blob, bd);
+}