diff options
| author | Tony O'Brien | 2016-12-02 09:22:34 +1300 |
|---|---|---|
| committer | York Sun | 2017-01-24 13:28:31 -0800 |
| commit | 09bfd962bdc97359b916bfbf18a17e2a85396d65 (patch) | |
| tree | f10f742b21bd31dbd0d35b97064913d5630091db /drivers/pci | |
| parent | 06ad970b53a3d6aa122685e6142a04908434a8ef (diff) | |
mpc85xx: pcie: Implement workaround for Erratum A007815
The read-only-write-enable bit is set by default and must be cleared
to prevent overwriting read-only registers. This should be done
immediately after resetting the PCI Express controller.
Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz>
[York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/fsl_pci_init.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 52792dcd597..af20cf0f3e7 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); } +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + /* The Read-Only Write Enable bit defaults to 1 instead of 0. + * Set to 0 to protect the read-only registers. + */ + clrbits_be32(&pci->dbi_ro_wr_en, 0x01); +#endif + /* Use generic setup_device to initialize standard pci regs, * but do not allocate any windows since any BAR found (such * as PCSRBAR) is not in this cpu's memory space. |