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authorPali Rohár2021-10-22 16:22:09 +0200
committerStefan Roese2021-11-03 06:45:26 +0100
commit657177ad8e240ea520eba26da5c0ba47bd935787 (patch)
tree5619cd3ba138948d2f14bb2b26f3044ecaa5fdb0 /drivers/pci
parentdaa9bfdb9cff9cc7ff0ad93383bbaf2bd618ab5e (diff)
pci: pci_mvebu: Fix read_config() with PCI_SIZE_8 or PCI_SIZE_16
When reading 8 or 16 bits from config space, use appropriate readb() or readw() calls. This ensures that PCIe controller does not read more bits from endpoint card as asked by read_config() function. Technically there should not be an issue with reading data from config space which are not later used as there are no clear-by-read registers. But it is better to use correct read operation based on requested size. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pci_mvebu.c17
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 8175511514a..3991086e0d2 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -184,9 +184,22 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
/* read data */
- data = readl(pcie->base + PCIE_CONF_DATA_OFF);
+ switch (size) {
+ case PCI_SIZE_8:
+ data = readb(pcie->base + PCIE_CONF_DATA_OFF + (offset & 3));
+ break;
+ case PCI_SIZE_16:
+ data = readw(pcie->base + PCIE_CONF_DATA_OFF + (offset & 2));
+ break;
+ case PCI_SIZE_32:
+ data = readl(pcie->base + PCIE_CONF_DATA_OFF);
+ break;
+ default:
+ return -EINVAL;
+ }
+
debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data);
- *valuep = pci_conv_32_to_size(data, offset, size);
+ *valuep = data;
return 0;
}