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authorMarek BehĂșn2018-04-24 17:21:12 +0200
committerStefan Roese2018-05-14 10:00:15 +0200
commitfae82c8f83b278c81ad707a133bb2c11bcd12276 (patch)
treea1276af8ea13bcca78d95f7c2a9e0449a6b8a1af /drivers/phy/marvell/comphy_a3700.h
parent62d77cea31216cad526e5f45c88e8377efc6fcae (diff)
phy: marvell: a3700: Change return type of macro MVEBU_REG
All the calls to reg_set and friends have to cast the first argument to void __iomem *. Lets change the return type of the MVEBU_REG macro instead. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/phy/marvell/comphy_a3700.h')
-rw-r--r--drivers/phy/marvell/comphy_a3700.h8
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h
index 322fc371f19..d41a1aa5162 100644
--- a/drivers/phy/marvell/comphy_a3700.h
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -9,7 +9,8 @@
#include "comphy.h"
#include "comphy_hpipe.h"
-#define MVEBU_REG(offs) ((uintptr_t)MVEBU_REGISTER(offs))
+#define MVEBU_REG(offs) \
+ ((void __iomem *)(ulong)MVEBU_REGISTER(offs))
#define DEFAULT_REFCLK_MHZ 25
#define PLL_SET_DELAY_US 600
@@ -60,11 +61,12 @@
#define USB3PHY_SHFT 2
#define SGMIIPHY_BASE(l) (l == 1 ? USB3PHY_BASE : PCIEPHY_BASE)
-#define SGMIIPHY_ADDR(l, a) (((a & 0x00007FF) * 2) | SGMIIPHY_BASE(l))
+#define SGMIIPHY_ADDR(l, a) \
+ ((void __iomem *)(((a & 0x00007FF) * 2) + SGMIIPHY_BASE(l)))
#define phy_read16(l, a) read16((void __iomem *)SGMIIPHY_ADDR(l, a))
#define phy_write16(l, a, data, mask) \
- reg_set16((void __iomem *)SGMIIPHY_ADDR(l, a), data, mask)
+ reg_set16(SGMIIPHY_ADDR(l, a), data, mask)
/* units */
#define PCIE 1