Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86

- New timer API to allow delays with a 32-bit microsecond timer
- Add dynamic ACPI structs (DSDT/SSDT) generations to the DM core
- x86: Enable ACPI table generation by default
- x86: Enable the copy framebuffer on Coral
- x86: A few fixes to FSP2 with ApolloLake
- x86: Drop setup_pcat_compatibility()
- x86: Primary-to-Sideband Bus minor fixes

3 files changed, 27 insertions, 10 deletions

diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index e62a2e03494..1acc5dabb01 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -15,6 +15,18 @@ config INTEL_PINCTRL_IOSTANDBY
 	bool
 	default y
 
+config INTEL_PINCTRL_MULTI_ACPI_DEVICES
+	bool
+	default y
+	help
+	  Enable this if the pinctrl devices are modelled as multiple,
+	  separate ACPI devices in the ACPI tables. If enabled, the ACPI
+	  devices match the U-Boot pinctrl devices and the pin 'offset' is
+	  relatove to a particular pinctrl device. If disabled, there is a
+	  single ACPI pinctrl device which includes all U-Boot pinctrl devices
+	  and the pin 'offset' is in effect a global pin number.
+
+
 config PINCTRL_INTEL_APL
 	bool "Support Intel Apollo Lake (APL)"
 	help
diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c
index ba8206350ea..ba21c9dcc2e 100644
--- a/drivers/pinctrl/intel/pinctrl.c
+++ b/drivers/pinctrl/intel/pinctrl.c
@@ -394,7 +394,7 @@ static int pinctrl_configure_pad(struct udevice *dev,
 	return 0;
 }
 
-u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset)
+u32 intel_pinctrl_get_config_reg_offset(struct udevice *dev, uint offset)
 {
 	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
 	const struct pad_community *comm = priv->comm;
@@ -407,9 +407,16 @@ u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset)
 	return config_offset;
 }
 
+u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset)
+{
+	uint config_offset = intel_pinctrl_get_config_reg_offset(dev, offset);
+
+	return (u32)(ulong)pcr_reg_address(dev, config_offset);
+}
+
 u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset)
 {
-	uint config_offset = intel_pinctrl_get_config_reg_addr(dev, offset);
+	uint config_offset = intel_pinctrl_get_config_reg_offset(dev, offset);
 
 	return pcr_read32(dev, config_offset);
 }
@@ -420,6 +427,8 @@ int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset)
 	const struct pad_community *comm = priv->comm;
 	int group;
 
+	if (IS_ENABLED(CONFIG_INTEL_PINCTRL_MULTI_ACPI_DEVICES))
+		return offset;
 	group = pinctrl_group_index(comm, offset);
 
 	/* If pad base is not set then use GPIO number as ACPI pin number */
@@ -610,15 +619,11 @@ int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
 {
 	struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
 	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
-	int ret;
 
 	if (!comm) {
 		log_err("Cannot find community for pid %d\n", pplat->pid);
 		return -EDOM;
 	}
-	ret = irq_first_device_type(X86_IRQT_ITSS, &priv->itss);
-	if (ret)
-		return log_msg_ret("Cannot find ITSS", ret);
 	priv->comm = comm;
 	priv->num_cfgs = num_cfgs;
 
@@ -628,8 +633,12 @@ int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
 int intel_pinctrl_probe(struct udevice *dev)
 {
 	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+	int ret;
 
 	priv->itss_pol_cfg = true;
+	ret = irq_first_device_type(X86_IRQT_ITSS, &priv->itss);
+	if (ret)
+		return log_msg_ret("Cannot find ITSS", ret);
 
 	return 0;
 }
diff --git a/drivers/pinctrl/intel/pinctrl_apl.c b/drivers/pinctrl/intel/pinctrl_apl.c
index c14176d4a77..7624a9974fe 100644
--- a/drivers/pinctrl/intel/pinctrl_apl.c
+++ b/drivers/pinctrl/intel/pinctrl_apl.c
@@ -75,7 +75,6 @@ static const struct pad_community apl_gpio_communities[] = {
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 		.name = "GPIO_GPE_N",
-		.acpi_path = "\\_SB.GPO0",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 		.groups = apl_community_n_groups,
@@ -94,7 +93,6 @@ static const struct pad_community apl_gpio_communities[] = {
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 		.name = "GPIO_GPE_NW",
-		.acpi_path = "\\_SB.GPO1",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 		.groups = apl_community_nw_groups,
@@ -113,7 +111,6 @@ static const struct pad_community apl_gpio_communities[] = {
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 		.name = "GPIO_GPE_W",
-		.acpi_path = "\\_SB.GPO2",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 		.groups = apl_community_w_groups,
@@ -132,7 +129,6 @@ static const struct pad_community apl_gpio_communities[] = {
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 		.name = "GPIO_GPE_SW",
-		.acpi_path = "\\_SB.GPO3",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 		.groups = apl_community_sw_groups,