diff options
author | Ramon Fried | 2018-05-16 12:13:42 +0300 |
---|---|---|
committer | Tom Rini | 2018-05-26 18:19:17 -0400 |
commit | b460b889e28379014a7f951c08d93a151116b1ad (patch) | |
tree | 4f6d12287cc923c0ff1966290193baebd2ed735a /drivers/serial/serial_msm.c | |
parent | 9558ddab96edbe98d26a258dbbde6f62be346dc5 (diff) |
serial: serial_msm: added pinmux & config
Serial port configuration was missing from previous implementation.
It only worked because it was preconfigured by LK.
This patch configures the uart for 115200 8N1.
It also configures the pin mux for uart pins using DT bindings.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Diffstat (limited to 'drivers/serial/serial_msm.c')
-rw-r--r-- | drivers/serial/serial_msm.c | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index a4279accb4f..c462394dbdc 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -16,6 +16,7 @@ #include <watchdog.h> #include <asm/io.h> #include <linux/compiler.h> +#include <dm/pinctrl.h> /* Serial registers - this driver works in uartdm mode*/ @@ -25,6 +26,9 @@ #define UARTDM_RXFS 0x50 /* RX channel status register */ #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */ #define UARTDM_RXFS_BUF_MASK 0x7 +#define UARTDM_MR1 0x00 +#define UARTDM_MR2 0x04 +#define UARTDM_CSR 0xA0 #define UARTDM_SR 0xA4 /* Status register */ #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */ @@ -45,6 +49,10 @@ #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ #define UARTDM_RF 0x140 /* UART Receive FIFO register */ +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC +#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 +#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 +#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 DECLARE_GLOBAL_DATA_PTR; @@ -179,6 +187,14 @@ static int msm_uart_clk_init(struct udevice *dev) return 0; } +static void uart_dm_init(struct msm_serial_data *priv) +{ + writel(UART_DM_CLK_RX_TX_BIT_RATE, priv->base + UARTDM_CSR); + writel(0x0, priv->base + UARTDM_MR1); + writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); + writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); + writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); +} static int msm_serial_probe(struct udevice *dev) { int ret; @@ -192,12 +208,8 @@ static int msm_serial_probe(struct udevice *dev) if (ret) return ret; - if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN) - writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR); - - writel(0, priv->base + UARTDM_IMR); - writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, priv->base + UARTDM_CR); - msm_serial_fetch(dev); + pinctrl_select_state(dev, "uart"); + uart_dm_init(priv); return 0; } |