diff options
| author | Tom Rini | 2022-06-27 10:15:50 -0400 |
|---|---|---|
| committer | Tom Rini | 2022-06-27 10:15:50 -0400 |
| commit | c316ee674f25b73285f241ce922307296616a92a (patch) | |
| tree | 9067e60451612dee5fbd0d3132548d3e84063f53 /drivers/serial | |
| parent | 31016a5a853cb5b8e27e9fdf956d8250ae59eca9 (diff) | |
| parent | 728a86edb63a647e6faf211c0dbc7bd0e4ff7ac6 (diff) | |
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2022.10
cpu:
- Add driver for microblaze cpu
net:
- Add support for DM_ETH_PHY to AXI emac and emaclite
xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS
zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize
versal:
- Enable loading app at EL1
serial:
- Setup default address and clock rates for DEBUG uarts
pinctrl:
- Add support for tri state and output enable properties
relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze
microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support
timer:
- Extract axi timer driver from Microblaze to generic location
Diffstat (limited to 'drivers/serial')
| -rw-r--r-- | drivers/serial/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 45c284a408d..f585622fdb7 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -476,6 +476,8 @@ config DEBUG_UART_BASE depends on DEBUG_UART default 0 if DEBUG_SBI_CONSOLE default 0 if DEBUG_UART_SANDBOX + default 0xff000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP + default 0xe0000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ help This is the base address of your UART for memory-mapped UARTs. @@ -502,6 +504,8 @@ config DEBUG_UART_CLOCK default 0 if DEBUG_SBI_CONSOLE default 0 if DEBUG_UART_SANDBOX default 0 if DEBUG_MVEBU_A3700_UART + default 100000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP + default 50000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ help The UART input clock determines the speed of the internal UART circuitry. The baud rate is derived from this by dividing the input |