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authorAtish Patra2019-02-25 08:15:08 +0000
committerAndes2019-02-27 09:12:33 +0800
commitee0633ef8b027960bd53ab62abb6f6fc25b1c66b (patch)
tree5a0c2f82bc53413bf9a5130e2839dd4089ec4c85 /drivers/serial
parenta3682008a03c0d4a58bcf62ca1e4a37187c9a8df (diff)
drivers: serial_sifive: Skip baudrate config if no input clock
It is possible that input clock is not available because clk device was not available and 'clock-frequency' DT property is also not available. In this case, instead of failing we should just skip baudrate config by returning zero. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/serial_sifive.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
index ea4d35d48c0..537bc7a975b 100644
--- a/drivers/serial/serial_sifive.c
+++ b/drivers/serial/serial_sifive.c
@@ -99,27 +99,27 @@ static int _sifive_serial_getc(struct uart_sifive *regs)
static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
{
- int err;
+ int ret;
struct clk clk;
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+ u32 clock = 0;
- err = clk_get_by_index(dev, 0, &clk);
- if (!err) {
- err = clk_get_rate(&clk);
- if (!IS_ERR_VALUE(err))
- platdata->clock = err;
- } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (IS_ERR_VALUE(ret)) {
debug("SiFive UART failed to get clock\n");
- return err;
- }
-
- if (!platdata->clock)
- platdata->clock = dev_read_u32_default(dev, "clock-frequency", 0);
- if (!platdata->clock) {
- debug("SiFive UART clock not defined\n");
- return -EINVAL;
+ ret = dev_read_u32(dev, "clock-frequency", &clock);
+ if (IS_ERR_VALUE(ret)) {
+ debug("SiFive UART clock not defined\n");
+ return 0;
+ }
+ } else {
+ clock = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(clock)) {
+ debug("SiFive UART clock get rate failed\n");
+ return 0;
+ }
}
-
+ platdata->clock = clock;
_sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate);
return 0;