diff options
| author | Stephen Warren | 2016-08-18 10:53:33 -0600 |
|---|---|---|
| committer | Tom Warren | 2016-08-25 15:35:03 -0700 |
| commit | 4832c7f5f79feebf8549f33c7257dec47c336470 (patch) | |
| tree | e55bdd0e4a8cf851821441258c3725b768651cab /drivers/spi/tegra210_qspi.c | |
| parent | 6002c75c59249aacb0a4a105d2b6ef1b3236e37f (diff) | |
spi: tegra: fix hang in set_mode()
In tegra20_slink.c, the set_mode() function may be executed before the
SPI bus is claimed the first time, and hence the clocks to the SPI
controller may not be running. If so, any register read/write at this
time will hang the CPU. Fix this by ensuring the clock is running as soon
as the driver is probed. This is observed on the Tegra30 Beaver board.
Apply the same clock initialization fix to all other Tegra SPI drivers so
that if set_mode() is ever implemented there, the same bug will not appear.
Note that tegra114_spi.c already operates in this fashion.
The clock manipulation code is copied from claim_bus() to probe() rather
than moved. This ensures that any calls to set_speed() take effect; the
clock can't be set once during probe and left unchanged.
Fixes: 5cb1b7b395c0 ("spi: tegra20: Add support for mode selection")
Cc: Mirza Krak <mirza.krak@hostmobility.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'drivers/spi/tegra210_qspi.c')
| -rw-r--r-- | drivers/spi/tegra210_qspi.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c index 6bbbe938395..026cff0c152 100644 --- a/drivers/spi/tegra210_qspi.c +++ b/drivers/spi/tegra210_qspi.c @@ -131,6 +131,9 @@ static int tegra210_qspi_probe(struct udevice *bus) priv->freq = plat->frequency; priv->periph_id = plat->periph_id; + /* Change SPI clock to correct frequency, PLLP_OUT0 source */ + clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); + return 0; } |