diff options
| author | Bin Meng | 2023-06-21 23:11:44 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang | 2023-07-12 13:21:40 +0800 |
| commit | 5764acb2617658af76c25285685e791ce6d0b051 (patch) | |
| tree | db44e07045cc57d1888f8efed317f5228f1423c1 /drivers/timer | |
| parent | c9745365f516a361be9cbe3568d2b8608084bbbf (diff) | |
riscv: timer: Update the sifive clint timer driver to support aclint
This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'drivers/timer')
| -rw-r--r-- | drivers/timer/sifive_clint_timer.c | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c index 939b99d937d..be45f17ddfb 100644 --- a/drivers/timer/sifive_clint_timer.c +++ b/drivers/timer/sifive_clint_timer.c @@ -12,12 +12,16 @@ #include <dm/device-internal.h> #include <linux/err.h> +#define CLINT_MTIME_OFFSET 0xbff8 +#define ACLINT_MTIME_OFFSET 0 + /* mtime register */ -#define MTIME_REG(base) ((ulong)(base) + 0xbff8) +#define MTIME_REG(base, offset) ((ulong)(base) + (offset)) static u64 notrace sifive_clint_get_count(struct udevice *dev) { - return readq((void __iomem *)MTIME_REG(dev_get_priv(dev))); + return readq((void __iomem *)MTIME_REG(dev_get_priv(dev), + dev_get_driver_data(dev))); } #if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) @@ -35,7 +39,8 @@ unsigned long notrace timer_early_get_rate(void) */ u64 notrace timer_early_get_count(void) { - return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE)); + return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE, + RISCV_MMODE_TIMEROFF)); } #endif @@ -53,8 +58,9 @@ static int sifive_clint_probe(struct udevice *dev) } static const struct udevice_id sifive_clint_ids[] = { - { .compatible = "riscv,clint0" }, - { .compatible = "sifive,clint0" }, + { .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET }, + { .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET }, + { .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET }, { } }; |