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authorTom Rini2019-11-23 20:50:11 -0500
committerTom Rini2019-11-23 20:50:11 -0500
commit9a0cbae22a613dfd55e15565785749b74c19fdf0 (patch)
treee66f4ce35ba9d7ce812b95b8b441fc0bec917a4f /drivers/usb/dwc3/core.c
parentc8f2fe4e670c91172540ab36700d7a8411fc6f76 (diff)
parent8019d32c4701b95410113541deb7f28d5c2b02a5 (diff)
Merge tag 'u-boot-rockchip-20191124' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Clean vid/pid in Kconfig and add fastboot for rk3399 - add 'u-boot, spl-fifo-mode' for mmc - Use FIT generator for rk3229 optee and rk3368 ATF - fan53555: add support for Silergy SYR82X and SYR83X
Diffstat (limited to 'drivers/usb/dwc3/core.c')
-rw-r--r--drivers/usb/dwc3/core.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 23af60c98d3..f779562de2e 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -613,6 +613,31 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
dwc3_gadget_run(dwc);
}
+static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
+ struct dwc3 *dwc)
+{
+ enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
+ u32 reg;
+
+ /* Set dwc3 usb2 phy config */
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+ reg |= DWC3_GUSB2PHYCFG_PHYIF;
+ reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
+
+ switch (hsphy_mode) {
+ case USBPHY_INTERFACE_MODE_UTMI:
+ reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
+ break;
+ case USBPHY_INTERFACE_MODE_UTMIW:
+ reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
+ break;
+ default:
+ break;
+ }
+
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+}
+
#define DWC3_ALIGN_MASK (16 - 1)
/**
@@ -721,6 +746,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
goto err0;
}
+ dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
+
ret = dwc3_event_buffers_setup(dwc);
if (ret) {
dev_err(dwc->dev, "failed to setup event buffers\n");