diff options
| author | Anton Schubert | 2015-07-23 15:02:09 +0200 |
|---|---|---|
| committer | Luka Perkov | 2015-08-17 18:49:15 +0200 |
| commit | 8a3337161d0fdedcfbe6d6be884f811496feedc1 (patch) | |
| tree | 1c4e4a479488535776912940d64b6de06aba58b4 /drivers/usb/host/ehci-marvell.c | |
| parent | 49114c87381accd930985a38413b73dda3f5357e (diff) | |
arm: mvebu: add multiple usb-hostcontroller support for AXP
This patch adds support for multiple hostcontrollers to the ehci-marvell driver
and enables all 3 usb-hcs on the db-mv784mp-gp board.
It depends on the initial Armada XP usb support patch from Stefan.
Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Diffstat (limited to 'drivers/usb/host/ehci-marvell.c')
| -rw-r--r-- | drivers/usb/host/ehci-marvell.c | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index fda812e94c5..50fa01c0798 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -38,13 +38,14 @@ DECLARE_GLOBAL_DATA_PTR; #define MVUSB0_BASE \ (mvebu_soc_family() == MVEBU_SOC_A38X ? \ MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE) +#define MVUSB_BASE(port) MVUSB0_BASE + ((port) << 12) /* * Once all the older Marvell SoC's (Orion, Kirkwood) are converted * to the common mvebu archticture including the mbus setup, this * will be the only function needed to configure the access windows */ -static void usb_brg_adrdec_setup(void) +static void usb_brg_adrdec_setup(int index) { const struct mbus_dram_target_info *dram; int i; @@ -52,8 +53,8 @@ static void usb_brg_adrdec_setup(void) dram = mvebu_mbus_dram_info(); for (i = 0; i < 4; i++) { - writel(0, MVUSB0_BASE + USB_WINDOW_CTRL(i)); - writel(0, MVUSB0_BASE + USB_WINDOW_BASE(i)); + writel(0, MVUSB_BASE(index) + USB_WINDOW_CTRL(i)); + writel(0, MVUSB_BASE(index) + USB_WINDOW_BASE(i)); } for (i = 0; i < dram->num_cs; i++) { @@ -62,14 +63,16 @@ static void usb_brg_adrdec_setup(void) /* Write size, attributes and target id to control register */ writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | (dram->mbus_dram_target_id << 4) | 1, - MVUSB0_BASE + USB_WINDOW_CTRL(i)); + MVUSB_BASE(index) + USB_WINDOW_CTRL(i)); /* Write base address to base register */ - writel(cs->base, MVUSB0_BASE + USB_WINDOW_BASE(i)); + writel(cs->base, MVUSB_BASE(index) + USB_WINDOW_BASE(i)); } } #else -static void usb_brg_adrdec_setup(void) +#define MVUSB_BASE(port) MVUSB0_BASE + +static void usb_brg_adrdec_setup(int index) { int i; u32 size, base, attrib; @@ -118,9 +121,9 @@ static void usb_brg_adrdec_setup(void) int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - usb_brg_adrdec_setup(); + usb_brg_adrdec_setup(index); - *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100); + *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100); *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); |