diff options
| author | Eric Nelson | 2012-09-21 07:33:51 +0000 |
|---|---|---|
| committer | Tom Rini | 2012-10-15 11:54:08 -0700 |
| commit | 0bb7e316f0ba1899ef2e94d75510c043683c212f (patch) | |
| tree | fa00e9103cf0a7e45ca6a826d16d36b18f276541 /drivers/video/ipu_common.c | |
| parent | e72d617860f7833756acddaf09ac28a3d8986d4c (diff) | |
i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fields
Add meaningful constants for each clock channels and use them for
enabling and disabling i.MX6 clocks.
Includes an update to enable/disable the IPU1 clock in
drivers/video/ipu_common to remove IMX5x register access
when used on i.MX6 as discussed in V1:
http://patchwork.ozlabs.org/patch/185129/
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Diffstat (limited to 'drivers/video/ipu_common.c')
| -rw-r--r-- | drivers/video/ipu_common.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index 2020da98d23..cc8f881a2d0 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -163,13 +163,13 @@ int clk_set_parent(struct clk *clk, struct clk *parent) static int clk_ipu_enable(struct clk *clk) { -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) u32 reg; reg = __raw_readl(clk->enable_reg); reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; __raw_writel(reg, clk->enable_reg); +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) /* Handshake with IPU when certain clock rates are changed. */ reg = __raw_readl(&mxc_ccm->ccdr); reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; @@ -185,13 +185,13 @@ static int clk_ipu_enable(struct clk *clk) static void clk_ipu_disable(struct clk *clk) { -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) u32 reg; reg = __raw_readl(clk->enable_reg); reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); __raw_writel(reg, clk->enable_reg); +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) /* * No handshake with IPU whe dividers are changed * as its not enabled. @@ -211,9 +211,15 @@ static void clk_ipu_disable(struct clk *clk) static struct clk ipu_clk = { .name = "ipu_clk", .rate = CONFIG_IPUV3_CLK, +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) .enable_reg = (u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR5)), .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET, +#else + .enable_reg = (u32 *)(CCM_BASE_ADDR + + offsetof(struct mxc_ccm_reg, CCGR3)), + .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET, +#endif .enable = clk_ipu_enable, .disable = clk_ipu_disable, .usecount = 0, |