Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

- dts clean up to use -u-boot for px30, rk3399 boards
- dts sycn from upstream kernel for rk3328, rk3399
- add rockchip rng driver
- new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB

9 files changed, 246 insertions, 19 deletions

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 1f623765956..d822acace14 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -996,6 +996,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 		break;
 	case ACLK_VOP1:
 	case HCLK_VOP1:
+	case HCLK_SD:
 		/**
 		 * assigned-clocks handling won't require for vopl, so
 		 * return 0 to satisfy clk_set_defaults during device probe.
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index edb6152bb9d..e4b22d79ebc 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -31,4 +31,12 @@ config RNG_STM32MP1
 	help
 	  Enable STM32MP1 rng driver.
 
+config RNG_ROCKCHIP
+	bool "Enable random number generator for rockchip crypto rng"
+	depends on ARCH_ROCKCHIP && DM_RNG
+	default n
+	help
+	  Enable random number generator for rockchip.This driver is
+	  support rng module of crypto v1 and crypto v2.
+
 endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 6a8a66779b5..44a00039173 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_DM_RNG) += rng-uclass.o
 obj-$(CONFIG_RNG_MESON) += meson-rng.o
 obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
 obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
+obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c
new file mode 100644
index 00000000000..47fb140077d
--- /dev/null
+++ b/drivers/rng/rockchip_rng.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ */
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <linux/iopoll.h>
+#include <linux/string.h>
+#include <rng.h>
+
+#define RK_HW_RNG_MAX 32
+
+#define _SBF(s, v)	((v) << (s))
+
+/* start of CRYPTO V1 register define */
+#define CRYPTO_V1_CTRL				0x0008
+#define CRYPTO_V1_RNG_START			BIT(8)
+#define CRYPTO_V1_RNG_FLUSH			BIT(9)
+
+#define CRYPTO_V1_TRNG_CTRL			0x0200
+#define CRYPTO_V1_OSC_ENABLE			BIT(16)
+#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x)		(x)
+
+#define CRYPTO_V1_TRNG_DOUT_0			0x0204
+/* end of CRYPTO V1 register define */
+
+/* start of CRYPTO V2 register define */
+#define CRYPTO_V2_RNG_CTL			0x0400
+#define CRYPTO_V2_RNG_64_BIT_LEN		_SBF(4, 0x00)
+#define CRYPTO_V2_RNG_128_BIT_LEN		_SBF(4, 0x01)
+#define CRYPTO_V2_RNG_192_BIT_LEN		_SBF(4, 0x02)
+#define CRYPTO_V2_RNG_256_BIT_LEN		_SBF(4, 0x03)
+#define CRYPTO_V2_RNG_FATESY_SOC_RING		_SBF(2, 0x00)
+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0		_SBF(2, 0x01)
+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1		_SBF(2, 0x02)
+#define CRYPTO_V2_RNG_SLOWEST_SOC_RING		_SBF(2, 0x03)
+#define CRYPTO_V2_RNG_ENABLE			BIT(1)
+#define CRYPTO_V2_RNG_START			BIT(0)
+#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0404
+#define CRYPTO_V2_RNG_DOUT_0			0x0410
+/* end of CRYPTO V2 register define */
+
+#define RK_RNG_TIME_OUT	50000  /* max 50ms */
+
+struct rk_rng_soc_data {
+	int (*rk_rng_read)(struct udevice *dev, void *data, size_t len);
+};
+
+struct rk_rng_platdata {
+	fdt_addr_t base;
+	struct rk_rng_soc_data *soc_data;
+};
+
+static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size)
+{
+	u32 count = RK_HW_RNG_MAX / sizeof(u32);
+	u32 reg, tmp_len;
+
+	if (size > RK_HW_RNG_MAX)
+		return -EINVAL;
+
+	while (size && count) {
+		reg = readl(addr);
+		tmp_len = min(size, sizeof(u32));
+		memcpy(buf, &reg, tmp_len);
+		addr += sizeof(u32);
+		buf += tmp_len;
+		size -= tmp_len;
+		count--;
+	}
+
+	return 0;
+}
+
+static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	struct rk_rng_platdata *pdata = dev_get_priv(dev);
+	u32 reg = 0;
+	int retval;
+
+	if (len > RK_HW_RNG_MAX)
+		return -EINVAL;
+
+	/* enable osc_ring to get entropy, sample period is set as 100 */
+	writel(CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100),
+	       pdata->base + CRYPTO_V1_TRNG_CTRL);
+
+	rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START,
+		     CRYPTO_V1_RNG_START);
+
+	retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg,
+				    !(reg & CRYPTO_V1_RNG_START),
+				    RK_RNG_TIME_OUT);
+	if (retval)
+		goto exit;
+
+	rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len);
+
+exit:
+	/* close TRNG */
+	rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START);
+
+	return 0;
+}
+
+static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	struct rk_rng_platdata *pdata = dev_get_priv(dev);
+	u32 reg = 0;
+	int retval;
+
+	if (len > RK_HW_RNG_MAX)
+		return -EINVAL;
+
+	/* enable osc_ring to get entropy, sample period is set as 100 */
+	writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT);
+
+	reg |= CRYPTO_V2_RNG_256_BIT_LEN;
+	reg |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
+	reg |= CRYPTO_V2_RNG_ENABLE;
+	reg |= CRYPTO_V2_RNG_START;
+
+	rk_clrsetreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff, reg);
+
+	retval = readl_poll_timeout(pdata->base + CRYPTO_V2_RNG_CTL, reg,
+				    !(reg & CRYPTO_V2_RNG_START),
+				    RK_RNG_TIME_OUT);
+	if (retval)
+		goto exit;
+
+	rk_rng_read_regs(pdata->base + CRYPTO_V2_RNG_DOUT_0, data, len);
+
+exit:
+	/* close TRNG */
+	rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff);
+
+	return retval;
+}
+
+static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	unsigned char *buf = data;
+	unsigned int i;
+	int ret = -EIO;
+
+	struct rk_rng_platdata *pdata = dev_get_priv(dev);
+
+	if (!len)
+		return 0;
+
+	if (!pdata->soc_data || !pdata->soc_data->rk_rng_read)
+		return -EINVAL;
+
+	for (i = 0; i < len / RK_HW_RNG_MAX; i++, buf += RK_HW_RNG_MAX) {
+		ret = pdata->soc_data->rk_rng_read(dev, buf, RK_HW_RNG_MAX);
+		if (ret)
+			goto exit;
+	}
+
+	if (len % RK_HW_RNG_MAX)
+		ret = pdata->soc_data->rk_rng_read(dev, buf,
+						   len % RK_HW_RNG_MAX);
+
+exit:
+	return ret;
+}
+
+static int rockchip_rng_ofdata_to_platdata(struct udevice *dev)
+{
+	struct rk_rng_platdata *pdata = dev_get_priv(dev);
+
+	memset(pdata, 0x00, sizeof(*pdata));
+
+	pdata->base = (fdt_addr_t)dev_read_addr_ptr(dev);
+	if (!pdata->base)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int rockchip_rng_probe(struct udevice *dev)
+{
+	struct rk_rng_platdata *pdata = dev_get_priv(dev);
+
+	pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev);
+
+	return 0;
+}
+
+static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
+	.rk_rng_read = rk_v1_rng_read,
+};
+
+static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
+	.rk_rng_read = rk_v2_rng_read,
+};
+
+static const struct dm_rng_ops rockchip_rng_ops = {
+	.read = rockchip_rng_read,
+};
+
+static const struct udevice_id rockchip_rng_match[] = {
+	{
+		.compatible = "rockchip,cryptov1-rng",
+		.data = (ulong)&rk_rng_v1_soc_data,
+	},
+	{
+		.compatible = "rockchip,cryptov2-rng",
+		.data = (ulong)&rk_rng_v2_soc_data,
+	},
+	{},
+};
+
+U_BOOT_DRIVER(rockchip_rng) = {
+	.name = "rockchip-rng",
+	.id = UCLASS_RNG,
+	.of_match = rockchip_rng_match,
+	.ops = &rockchip_rng_ops,
+	.probe = rockchip_rng_probe,
+	.ofdata_to_platdata = rockchip_rng_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct rk_rng_platdata),
+};
diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c
index f4444b9c348..71d3faf169d 100644
--- a/drivers/video/rockchip/rk3288_mipi.c
+++ b/drivers/video/rockchip/rk3288_mipi.c
@@ -8,7 +8,6 @@
 #include <clk.h>
 #include <display.h>
 #include <dm.h>
-#include <fdtdec.h>
 #include <panel.h>
 #include <regmap.h>
 #include "rk_mipi.h"
diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c
index 74ebe770a95..cfaa37797ed 100644
--- a/drivers/video/rockchip/rk3399_mipi.c
+++ b/drivers/video/rockchip/rk3399_mipi.c
@@ -8,7 +8,6 @@
 #include <clk.h>
 #include <display.h>
 #include <dm.h>
-#include <fdtdec.h>
 #include <panel.h>
 #include <regmap.h>
 #include "rk_mipi.h"
diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
index cf84b886e72..99b16cd95ed 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -997,7 +997,7 @@ static int rk_edp_ofdata_to_platdata(struct udevice *dev)
 {
 	struct rk_edp_priv *priv = dev_get_priv(dev);
 
-	priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev);
+	priv->regs = dev_read_addr_ptr(dev);
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 
 	return 0;
diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c
index 79e24baf53b..c92c2e3c6c0 100644
--- a/drivers/video/rockchip/rk_lvds.c
+++ b/drivers/video/rockchip/rk_lvds.c
@@ -161,8 +161,7 @@ int rk_lvds_enable(struct udevice *dev, int panel_bpp,
 
 int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
 {
-	if (fdtdec_decode_display_timing
-	    (gd->fdt_blob, dev_of_offset(dev), 0, timing)) {
+	if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
 		debug("%s: Failed to decode display timing\n", __func__);
 		return -EINVAL;
 	}
@@ -173,13 +172,11 @@ int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
 static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
 {
 	struct rk_lvds_priv *priv = dev_get_priv(dev);
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(dev);
 	int ret;
-	priv->regs = (void *)devfdt_get_addr(dev);
+	priv->regs = dev_read_addr_ptr(dev);
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 
-	ret = fdtdec_get_int(blob, node, "rockchip,output", -1);
+	ret = dev_read_s32_default(dev, "rockchip,output", -1);
 	if (ret != -1) {
 		priv->output = ret;
 		debug("LVDS output : %d\n", ret);
@@ -188,7 +185,7 @@ static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
 		priv->output = LVDS_OUTPUT_RGB;
 	}
 
-	ret = fdtdec_get_int(blob, node, "rockchip,data-mapping", -1);
+	ret = dev_read_s32_default(dev, "rockchip,data-mapping", -1);
 	if (ret != -1) {
 		priv->format = ret;
 		debug("LVDS data-mapping : %d\n", ret);
@@ -197,7 +194,7 @@ static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
 		priv->format = LVDS_FORMAT_JEIDA;
 	}
 
-	ret = fdtdec_get_int(blob, node, "rockchip,data-width", -1);
+	ret = dev_read_s32_default(dev, "rockchip,data-width", -1);
 	if (ret != -1) {
 		debug("LVDS data-width : %d\n", ret);
 		if (ret == 24) {
diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
index f9280e86070..f1c21bb8d7e 100644
--- a/drivers/video/rockchip/rk_mipi.c
+++ b/drivers/video/rockchip/rk_mipi.c
@@ -8,7 +8,6 @@
 #include <clk.h>
 #include <display.h>
 #include <dm.h>
-#include <fdtdec.h>
 #include <panel.h>
 #include <regmap.h>
 #include "rk_mipi.h"
@@ -29,8 +28,7 @@ int rk_mipi_read_timing(struct udevice *dev,
 {
 	int ret;
 
-	ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
-					 0, timing);
+	ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timing);
 	if (ret) {
 		debug("%s: Failed to decode display timing (ret=%d)\n",
 		      __func__, ret);
@@ -77,7 +75,7 @@ static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val)
 int rk_mipi_dsi_enable(struct udevice *dev,
 		       const struct display_timing *timing)
 {
-	int node, timing_node;
+	ofnode node, timing_node;
 	int val;
 	struct rk_mipi_priv *priv = dev_get_priv(dev);
 	uintptr_t regs = priv->regs;
@@ -120,10 +118,10 @@ int rk_mipi_dsi_enable(struct udevice *dev,
 	rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0);
 
 	/* Set dpi color coding depth 24 bit */
-	timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),
-									 "display-timings");
-	node = fdt_first_subnode(gd->fdt_blob, timing_node);
-	val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);
+	timing_node = ofnode_find_subnode(dev->node, "display-timings");
+	node = ofnode_first_subnode(timing_node);
+
+	val = ofnode_read_u32_default(node, "bits-per-pixel", -1);
 	switch (val) {
 	case 16:
 		rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1);