Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi

- Toshiba spinand (Yoshio)
- SPI/SPI Flash cleanup (Jagan)
- Remove SH SPI (Jagan)

12 files changed, 167 insertions, 449 deletions

diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c
index c4beefa6176..c2cd3b426b3 100644
--- a/drivers/mtd/nand/spi/toshiba.c
+++ b/drivers/mtd/nand/spi/toshiba.c
@@ -23,13 +23,25 @@ static SPINAND_OP_VARIANTS(read_cache_variants,
 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
 
+static SPINAND_OP_VARIANTS(write_cache_x4_variants,
+		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_x4_variants,
+		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+/**
+ * Backward compatibility for 1st generation Serial NAND devices
+ * which don't support Quad Program Load operation.
+ */
 static SPINAND_OP_VARIANTS(write_cache_variants,
 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
 
 static SPINAND_OP_VARIANTS(update_cache_variants,
 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
 
-static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section,
+static int tx58cxgxsxraix_ooblayout_ecc(struct mtd_info *mtd, int section,
 				     struct mtd_oob_region *region)
 {
 	if (section > 0)
@@ -41,7 +53,7 @@ static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section,
 	return 0;
 }
 
-static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section,
+static int tx58cxgxsxraix_ooblayout_free(struct mtd_info *mtd, int section,
 				      struct mtd_oob_region *region)
 {
 	if (section > 0)
@@ -54,12 +66,12 @@ static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section,
 	return 0;
 }
 
-static const struct mtd_ooblayout_ops tc58cxgxsx_ooblayout = {
-	.ecc = tc58cxgxsx_ooblayout_ecc,
-	.rfree = tc58cxgxsx_ooblayout_free,
+static const struct mtd_ooblayout_ops tx58cxgxsxraix_ooblayout = {
+	.ecc = tx58cxgxsxraix_ooblayout_ecc,
+	.rfree = tx58cxgxsxraix_ooblayout_free,
 };
 
-static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand,
+static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
 				      u8 status)
 {
 	struct nand_device *nand = spinand_to_nand(spinand);
@@ -98,76 +110,151 @@ static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand,
 }
 
 static const struct spinand_info toshiba_spinand_table[] = {
-	/* 3.3V 1Gb */
-	SPINAND_INFO("TC58CVG0S3", 0xC2,
+	/* 3.3V 1Gb (1st generation) */
+	SPINAND_INFO("TC58CVG0S3HRAIG", 0xC2,
 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
 		     NAND_ECCREQ(8, 512),
 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 					      &write_cache_variants,
 					      &update_cache_variants),
 		     0,
-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
-				     tc58cxgxsx_ecc_get_status)),
-	/* 3.3V 2Gb */
-	SPINAND_INFO("TC58CVG1S3", 0xCB,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+	/* 3.3V 2Gb (1st generation) */
+	SPINAND_INFO("TC58CVG1S3HRAIG", 0xCB,
 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
 		     NAND_ECCREQ(8, 512),
 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 					      &write_cache_variants,
 					      &update_cache_variants),
 		     0,
-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
-				     tc58cxgxsx_ecc_get_status)),
-	/* 3.3V 4Gb */
-	SPINAND_INFO("TC58CVG2S0", 0xCD,
-		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
-		     NAND_ECCREQ(8, 512),
-		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-					      &write_cache_variants,
-					      &update_cache_variants),
-		     0,
-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
-				     tc58cxgxsx_ecc_get_status)),
-	/* 3.3V 4Gb */
-	SPINAND_INFO("TC58CVG2S0", 0xED,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+	/* 3.3V 4Gb (1st generation) */
+	SPINAND_INFO("TC58CVG2S0HRAIG", 0xCD,
 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
 		     NAND_ECCREQ(8, 512),
 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 					      &write_cache_variants,
 					      &update_cache_variants),
 		     0,
-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
-				     tc58cxgxsx_ecc_get_status)),
-	/* 1.8V 1Gb */
-	SPINAND_INFO("TC58CYG0S3", 0xB2,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+	/* 1.8V 1Gb (1st generation) */
+	SPINAND_INFO("TC58CYG0S3HRAIG", 0xB2,
 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
 		     NAND_ECCREQ(8, 512),
 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 					      &write_cache_variants,
 					      &update_cache_variants),
 		     0,
-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
-				     tc58cxgxsx_ecc_get_status)),
-	/* 1.8V 2Gb */
-	SPINAND_INFO("TC58CYG1S3", 0xBB,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+	/* 1.8V 2Gb (1st generation) */
+	SPINAND_INFO("TC58CYG1S3HRAIG", 0xBB,
 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
 		     NAND_ECCREQ(8, 512),
 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 					      &write_cache_variants,
 					      &update_cache_variants),
 		     0,
-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
-				     tc58cxgxsx_ecc_get_status)),
-	/* 1.8V 4Gb */
-	SPINAND_INFO("TC58CYG2S0", 0xBD,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+	/* 1.8V 4Gb (1st generation) */
+	SPINAND_INFO("TC58CYG2S0HRAIG", 0xBD,
 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
 		     NAND_ECCREQ(8, 512),
 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 					      &write_cache_variants,
 					      &update_cache_variants),
 		     0,
-		     SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
-				     tc58cxgxsx_ecc_get_status)),
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+
+	/*
+	 * 2nd generation serial nand has HOLD_D which is equivalent to
+	 * QE_BIT.
+	 */
+	/* 3.3V 1Gb (2nd generation) */
+	SPINAND_INFO("TC58CVG0S3HRAIJ", 0xE2,
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_x4_variants,
+					      &update_cache_x4_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+	/* 3.3V 2Gb (2nd generation) */
+	SPINAND_INFO("TC58CVG1S3HRAIJ", 0xEB,
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_x4_variants,
+					      &update_cache_x4_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+	/* 3.3V 4Gb (2nd generation) */
+	SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED,
+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_x4_variants,
+					      &update_cache_x4_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+	/* 3.3V 8Gb (2nd generation) */
+	SPINAND_INFO("TH58CVG3S0HRAIJ", 0xE4,
+		     NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_x4_variants,
+					      &update_cache_x4_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+	/* 1.8V 1Gb (2nd generation) */
+	SPINAND_INFO("TC58CYG0S3HRAIJ", 0xD2,
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_x4_variants,
+					      &update_cache_x4_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+	/* 1.8V 2Gb (2nd generation) */
+	SPINAND_INFO("TC58CYG1S3HRAIJ", 0xDB,
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_x4_variants,
+					      &update_cache_x4_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+	/* 1.8V 4Gb (2nd generation) */
+	SPINAND_INFO("TC58CYG2S0HRAIJ", 0xDD,
+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_x4_variants,
+					      &update_cache_x4_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
+	/* 1.8V 8Gb (2nd generation) */
+	SPINAND_INFO("TH58CYG3S0HRAIJ", 0xD4,
+		     NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_x4_variants,
+					      &update_cache_x4_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+				     tx58cxgxsxraix_ecc_get_status)),
 };
 
 static int toshiba_spinand_detect(struct spinand_device *spinand)
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index de369aa001d..9ce2ecb99ac 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -30,15 +30,6 @@ int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len)
 	return log_ret(sf_get_ops(dev)->erase(dev, offset, len));
 }
 
-int spl_flash_get_sw_write_prot(struct udevice *dev)
-{
-	struct dm_spi_flash_ops *ops = sf_get_ops(dev);
-
-	if (!ops->get_sw_write_prot)
-		return -ENOSYS;
-	return log_ret(ops->get_sw_write_prot(dev));
-}
-
 /*
  * TODO(sjg@chromium.org): This is an old-style function. We should remove
  * it when all SPI flash drivers use dm
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index ce0cf4c428b..dabd40a4cc1 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -75,12 +75,18 @@ extern const struct flash_info spi_nor_ids[];
 #define JEDEC_MFR(info)	((info)->id[0])
 #define JEDEC_ID(info)		(((info)->id[1]) << 8 | ((info)->id[2]))
 
-/* Get software write-protect value (BP bits) */
-int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);
-
-
 #if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
 int spi_flash_mtd_register(struct spi_flash *flash);
 void spi_flash_mtd_unregister(void);
+#else
+static inline int spi_flash_mtd_register(struct spi_flash *flash)
+{
+	return 0;
+}
+
+static inline void spi_flash_mtd_unregister(void)
+{
+}
 #endif
+
 #endif /* _SF_INTERNAL_H_ */
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index c2e51f9c68d..3548d6319b3 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -45,9 +45,8 @@ static int spi_flash_probe_slave(struct spi_flash *flash)
 	if (ret)
 		goto err_read_id;
 
-#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
-	ret = spi_flash_mtd_register(flash);
-#endif
+	if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
+		ret = spi_flash_mtd_register(flash);
 
 err_read_id:
 	spi_release_bus(spi);
@@ -84,9 +83,9 @@ struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
 
 void spi_flash_free(struct spi_flash *flash)
 {
-#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
-	spi_flash_mtd_unregister();
-#endif
+	if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
+		spi_flash_mtd_unregister();
+
 	spi_free_slave(flash->spi);
 	free(flash);
 }
@@ -131,31 +130,22 @@ static int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len)
 	return mtd->_erase(mtd, &instr);
 }
 
-static int spi_flash_std_get_sw_write_prot(struct udevice *dev)
-{
-	struct spi_flash *flash = dev_get_uclass_priv(dev);
-
-	return spi_flash_cmd_get_sw_write_prot(flash);
-}
-
 int spi_flash_std_probe(struct udevice *dev)
 {
 	struct spi_slave *slave = dev_get_parent_priv(dev);
-	struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
 	struct spi_flash *flash;
 
 	flash = dev_get_uclass_priv(dev);
 	flash->dev = dev;
 	flash->spi = slave;
-	debug("%s: slave=%p, cs=%d\n", __func__, slave, plat->cs);
 	return spi_flash_probe_slave(flash);
 }
 
 static int spi_flash_std_remove(struct udevice *dev)
 {
-#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
-	spi_flash_mtd_unregister();
-#endif
+	if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
+		spi_flash_mtd_unregister();
+
 	return 0;
 }
 
@@ -163,7 +153,6 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {
 	.read = spi_flash_std_read,
 	.write = spi_flash_std_write,
 	.erase = spi_flash_std_erase,
-	.get_sw_write_prot = spi_flash_std_get_sw_write_prot,
 };
 
 static const struct udevice_id spi_flash_std_ids[] = {
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 56b44ebbe8d..1e3f51d2acb 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1235,6 +1235,12 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
 	size_t page_offset, page_remain, i;
 	ssize_t ret;
 
+#ifdef CONFIG_SPI_FLASH_SST
+	/* sst nor chips use AAI word program */
+	if (nor->info->flags & SST_WRITE)
+		return sst_write(mtd, to, len, retlen, buf);
+#endif
+
 	dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
 
 	if (!len)
@@ -2530,6 +2536,7 @@ int spi_nor_scan(struct spi_nor *nor)
 	mtd->size = params.size;
 	mtd->_erase = spi_nor_erase;
 	mtd->_read = spi_nor_read;
+	mtd->_write = spi_nor_write;
 
 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
 	/* NOR protection support for STmicro/Micron chips and similar */
@@ -2553,13 +2560,7 @@ int spi_nor_scan(struct spi_nor *nor)
 		nor->flash_unlock = sst26_unlock;
 		nor->flash_is_locked = sst26_is_locked;
 	}
-
-	/* sst nor chips use AAI word program */
-	if (info->flags & SST_WRITE)
-		mtd->_write = sst_write;
-	else
 #endif
-		mtd->_write = spi_nor_write;
 
 	if (info->flags & USE_FSR)
 		nor->flags |= SNOR_F_USE_FSR;
@@ -2640,14 +2641,3 @@ int spi_nor_scan(struct spi_nor *nor)
 
 	return 0;
 }
-
-/* U-Boot specific functions, need to extend MTD to support these */
-int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
-{
-	int sr = read_sr(nor);
-
-	if (sr < 0)
-		return sr;
-
-	return (sr >> 2) & 7;
-}
diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c
index 55f86d51555..9f676c649d8 100644
--- a/drivers/mtd/spi/spi-nor-tiny.c
+++ b/drivers/mtd/spi/spi-nor-tiny.c
@@ -798,9 +798,3 @@ int spi_nor_scan(struct spi_nor *nor)
 
 	return 0;
 }
-
-/* U-Boot specific functions, need to extend MTD to support these */
-int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
-{
-	return -ENOTSUPP;
-}
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index dccd5ea0d9a..59415209ee4 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -141,6 +141,14 @@ config FSL_DSPI
 	  this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
 	  use this driver.
 
+config FSL_QSPI
+	bool "Freescale QSPI driver"
+	imply SPI_FLASH_BAR
+	help
+	  Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
+	  used to access the SPI NOR flash on platforms embedding this
+	  Freescale IP core.
+
 config ICH_SPI
 	bool "Intel ICH SPI driver"
 	help
@@ -167,6 +175,13 @@ config MPC8XXX_SPI
 	help
 	  Enable support for SPI on the MPC8XXX PowerPC SoCs.
 
+config MSCC_BB_SPI
+	bool "MSCC bitbang SPI driver"
+	depends on SOC_VCOREIII
+	help
+	  Enable MSCC bitbang SPI driver. This driver can be used on
+	  MSCC SOCs.
+
 config MT7621_SPI
 	bool "MediaTek MT7621 SPI driver"
 	depends on SOC_MT7628
@@ -377,19 +392,6 @@ config SOFT_SPI
 	 Enable Soft SPI driver. This driver is to use GPIO simulate
 	 the SPI protocol.
 
-config MSCC_BB_SPI
-	bool "MSCC bitbang SPI driver"
-	depends on SOC_VCOREIII
-	help
-	  Enable MSCC bitbang SPI driver. This driver can be used on
-	  MSCC SOCs.
-
-config CF_SPI
-	bool "ColdFire SPI driver"
-	help
-	  Enable the ColdFire SPI driver. This driver can be used on
-	  some m68k SoCs.
-
 config FSL_ESPI
 	bool "Freescale eSPI driver"
 	imply SPI_FLASH_BAR
@@ -398,27 +400,12 @@ config FSL_ESPI
 	  access the SPI interface and SPI NOR flash on platforms embedding
 	  this Freescale eSPI IP core.
 
-config FSL_QSPI
-	bool "Freescale QSPI driver"
-	imply SPI_FLASH_BAR
-	help
-	  Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
-	  used to access the SPI NOR flash on platforms embedding this
-	  Freescale IP core.
-
 config DAVINCI_SPI
 	bool "Davinci & Keystone SPI driver"
 	depends on ARCH_DAVINCI || ARCH_KEYSTONE
 	help
 	  Enable the Davinci SPI driver
 
-config SH_SPI
-	bool "SuperH SPI driver"
-	depends on DEPRECATED
-	help
-	  Enable the SuperH SPI controller driver. This driver can be used
-	  on various SuperH SoCs, such as SH7757.
-
 config SH_QSPI
 	bool "Renesas Quad SPI driver"
 	help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 6441694c8d8..342776404a5 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -52,7 +52,6 @@ obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
 obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
 obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
 obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o
-obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
 obj-$(CONFIG_STM32_SPI) += stm32_spi.o
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
index dd9c77281f1..dec92df69bd 100644
--- a/drivers/spi/cf_spi.c
+++ b/drivers/spi/cf_spi.c
@@ -383,10 +383,6 @@ static int coldfire_spi_probe(struct udevice *bus)
 	return 0;
 }
 
-void spi_init(void)
-{
-}
-
 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
 {
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 01fcf6bef5a..3986b06b25c 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -183,10 +183,6 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 }
 #endif
 
-void spi_init(void)
-{
-}
-
 void spi_cs_activate(struct spi_slave *slave)
 {
 	_spi_cs_activate(spireg);
diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c
deleted file mode 100644
index 4ecfe60115b..00000000000
--- a/drivers/spi/sh_spi.c
+++ /dev/null
@@ -1,250 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH SPI driver
- *
- * Copyright (C) 2011-2012 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <console.h>
-#include <malloc.h>
-#include <spi.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include "sh_spi.h"
-
-static void sh_spi_write(unsigned long data, unsigned long *reg)
-{
-	writel(data, reg);
-}
-
-static unsigned long sh_spi_read(unsigned long *reg)
-{
-	return readl(reg);
-}
-
-static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
-{
-	unsigned long tmp;
-
-	tmp = sh_spi_read(reg);
-	tmp |= val;
-	sh_spi_write(tmp, reg);
-}
-
-static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
-{
-	unsigned long tmp;
-
-	tmp = sh_spi_read(reg);
-	tmp &= ~val;
-	sh_spi_write(tmp, reg);
-}
-
-static void clear_fifo(struct sh_spi *ss)
-{
-	sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
-	sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
-}
-
-static int recvbuf_wait(struct sh_spi *ss)
-{
-	while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
-		if (ctrlc())
-			return 1;
-		udelay(10);
-	}
-	return 0;
-}
-
-static int write_fifo_empty_wait(struct sh_spi *ss)
-{
-	while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
-		if (ctrlc())
-			return 1;
-		udelay(10);
-	}
-	return 0;
-}
-
-static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
-{
-	unsigned long val = 0;
-
-	if (cs & 0x01)
-		val |= SH_SPI_SSS0;
-	if (cs & 0x02)
-		val |= SH_SPI_SSS1;
-
-	sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
-	sh_spi_set_bit(val, &ss->regs->cr4);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
-{
-	struct sh_spi *ss;
-
-	if (!spi_cs_is_valid(bus, cs))
-		return NULL;
-
-	ss = spi_alloc_slave(struct sh_spi, bus, cs);
-	if (!ss)
-		return NULL;
-
-	ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
-
-	/* SPI sycle stop */
-	sh_spi_write(0xfe, &ss->regs->cr1);
-	/* CR1 init */
-	sh_spi_write(0x00, &ss->regs->cr1);
-	/* CR3 init */
-	sh_spi_write(0x00, &ss->regs->cr3);
-	sh_spi_set_cs(ss, cs);
-
-	clear_fifo(ss);
-
-	/* 1/8 clock */
-	sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
-	udelay(10);
-
-	return &ss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct sh_spi *spi = to_sh_spi(slave);
-
-	free(spi);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-	return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-	struct sh_spi *ss = to_sh_spi(slave);
-
-	sh_spi_write(sh_spi_read(&ss->regs->cr1) &
-		~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1);
-}
-
-static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
-			unsigned int len, unsigned long flags)
-{
-	int i, cur_len, ret = 0;
-	int remain = (int)len;
-
-	if (len >= SH_SPI_FIFO_SIZE)
-		sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
-
-	while (remain > 0) {
-		cur_len = (remain < SH_SPI_FIFO_SIZE) ?
-				remain : SH_SPI_FIFO_SIZE;
-		for (i = 0; i < cur_len &&
-			!(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) &&
-			!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF);
-				i++)
-			sh_spi_write(tx_data[i], &ss->regs->tbr_rbr);
-
-		cur_len = i;
-
-		if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) {
-			/* Abort the transaction */
-			flags |= SPI_XFER_END;
-			sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4);
-			ret = 1;
-			break;
-		}
-
-		remain -= cur_len;
-		tx_data += cur_len;
-
-		if (remain > 0)
-			write_fifo_empty_wait(ss);
-	}
-
-	if (flags & SPI_XFER_END) {
-		sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
-		sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
-		udelay(100);
-		write_fifo_empty_wait(ss);
-	}
-
-	return ret;
-}
-
-static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
-			  unsigned int len, unsigned long flags)
-{
-	int i;
-
-	if (len > SH_SPI_MAX_BYTE)
-		sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
-	else
-		sh_spi_write(len, &ss->regs->cr3);
-
-	sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
-	sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
-
-	for (i = 0; i < len; i++) {
-		if (recvbuf_wait(ss))
-			return 0;
-
-		rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr);
-	}
-	sh_spi_write(0, &ss->regs->cr3);
-
-	return 0;
-}
-
-int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-		void *din, unsigned long flags)
-{
-	struct sh_spi *ss = to_sh_spi(slave);
-	const unsigned char *tx_data = dout;
-	unsigned char *rx_data = din;
-	unsigned int len = bitlen / 8;
-	int ret = 0;
-
-	if (flags & SPI_XFER_BEGIN)
-		sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA,
-				&ss->regs->cr1);
-
-	if (tx_data)
-		ret = sh_spi_send(ss, tx_data, len, flags);
-
-	if (ret == 0 && rx_data)
-		ret = sh_spi_receive(ss, rx_data, len, flags);
-
-	if (flags & SPI_XFER_END) {
-		sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1);
-		udelay(100);
-
-		sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD,
-				 &ss->regs->cr1);
-		clear_fifo(ss);
-	}
-
-	return ret;
-}
-
-int  spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	if (!bus && cs < SH_SPI_NUM_CS)
-		return 1;
-	else
-		return 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-
-}
diff --git a/drivers/spi/sh_spi.h b/drivers/spi/sh_spi.h
deleted file mode 100644
index 33a4630c8da..00000000000
--- a/drivers/spi/sh_spi.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * SH SPI driver
- *
- * Copyright (C) 2011 Renesas Solutions Corp.
- */
-
-#ifndef __SH_SPI_H__
-#define __SH_SPI_H__
-
-#include <spi.h>
-
-struct sh_spi_regs {
-	unsigned long tbr_rbr;
-	unsigned long resv1;
-	unsigned long cr1;
-	unsigned long resv2;
-	unsigned long cr2;
-	unsigned long resv3;
-	unsigned long cr3;
-	unsigned long resv4;
-	unsigned long cr4;
-};
-
-/* CR1 */
-#define SH_SPI_TBE	0x80
-#define SH_SPI_TBF	0x40
-#define SH_SPI_RBE	0x20
-#define SH_SPI_RBF	0x10
-#define SH_SPI_PFONRD	0x08
-#define SH_SPI_SSDB	0x04
-#define SH_SPI_SSD	0x02
-#define SH_SPI_SSA	0x01
-
-/* CR2 */
-#define SH_SPI_RSTF	0x80
-#define SH_SPI_LOOPBK	0x40
-#define SH_SPI_CPOL	0x20
-#define SH_SPI_CPHA	0x10
-#define SH_SPI_L1M0	0x08
-
-/* CR3 */
-#define SH_SPI_MAX_BYTE	0xFF
-
-/* CR4 */
-#define SH_SPI_TBEI	0x80
-#define SH_SPI_TBFI	0x40
-#define SH_SPI_RBEI	0x20
-#define SH_SPI_RBFI	0x10
-#define SH_SPI_SSS1	0x08
-#define SH_SPI_WPABRT	0x04
-#define SH_SPI_SSS0	0x01
-
-#define SH_SPI_FIFO_SIZE	32
-#define SH_SPI_NUM_CS		4
-
-struct sh_spi {
-	struct spi_slave	slave;
-	struct sh_spi_regs	*regs;
-};
-
-static inline struct sh_spi *to_sh_spi(struct spi_slave *slave)
-{
-	return container_of(slave, struct sh_spi, slave);
-}
-
-#endif