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authorTom Rini2022-10-24 21:28:14 -0400
committerTom Rini2022-10-24 21:28:14 -0400
commit26bfb853cae5c05950f8716e6f405eb0f9588d97 (patch)
tree6b633a5e3eb58f1a1c8b05d0f958faacabe30594 /drivers
parent7d8ab3cd635ba2a7faea9f12278ea200149c82aa (diff)
parent337af54a36c6409b7eeb49619c796178b3c22372 (diff)
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mmc/Kconfig4
-rw-r--r--drivers/mmc/dw_mmc.c3
-rw-r--r--drivers/mmc/f_sdh30.c66
-rw-r--r--drivers/mmc/ftsdc010_mci.c2
-rw-r--r--drivers/mmc/mmc.c6
-rw-r--r--drivers/mmc/sdhci.c8
-rw-r--r--drivers/mmc/stm32_sdmmc2.c20
7 files changed, 97 insertions, 12 deletions
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index f799f70e43a..56f42820c74 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -576,12 +576,12 @@ config MMC_SDHCI_IPROC
If unsure, say N.
config MMC_SDHCI_F_SDH30
- bool "SDHCI support for Fujitsu Semiconductor F_SDH30"
+ bool "SDHCI support for Fujitsu Semiconductor/Socionext F_SDH30"
depends on BLK && DM_MMC
depends on MMC_SDHCI
help
This selects the Secure Digital Host Controller Interface (SDHCI)
- Needed by some Fujitsu SoC for MMC / SD / SDIO support.
+ Needed by some Fujitsu/Socionext SoC for MMC / SD / SDIO support.
If you have a controller with this interface, say Y or M here.
If unsure, say N.
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 4232c5eb8c3..5085a3b491d 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -168,7 +168,8 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
if (data->flags == MMC_DATA_READ &&
(mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO))) {
dwmci_writel(host, DWMCI_RINTSTS,
- DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO);
+ mask & (DWMCI_INTMSK_RXDR |
+ DWMCI_INTMSK_DTO));
while (size) {
ret = dwmci_fifo_ready(host,
DWMCI_FIFO_EMPTY,
diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c
index 3a85d9e348a..3d587a464d5 100644
--- a/drivers/mmc/f_sdh30.c
+++ b/drivers/mmc/f_sdh30.c
@@ -11,13 +11,48 @@
#include <malloc.h>
#include <sdhci.h>
+#define F_SDH30_ESD_CONTROL 0x124
+#define F_SDH30_CMD_DAT_DELAY BIT(9)
+
+#define F_SDH30_TEST 0x158
+#define F_SDH30_FORCE_CARD_INSERT BIT(6)
+
+struct f_sdh30_data {
+ void (*init)(struct udevice *dev);
+ u32 quirks;
+};
+
struct f_sdh30_plat {
struct mmc_config cfg;
struct mmc mmc;
+
+ bool enable_cmd_dat_delay;
+ const struct f_sdh30_data *data;
};
DECLARE_GLOBAL_DATA_PTR;
+static void f_sdh30_e51_init(struct udevice *dev)
+{
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ u32 val;
+
+ val = sdhci_readl(host, F_SDH30_ESD_CONTROL);
+ if (plat->enable_cmd_dat_delay)
+ val |= F_SDH30_CMD_DAT_DELAY;
+ else
+ val &= ~F_SDH30_CMD_DAT_DELAY;
+ sdhci_writel(host, val, F_SDH30_ESD_CONTROL);
+
+ val = sdhci_readl(host, F_SDH30_TEST);
+ if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
+ val |= F_SDH30_FORCE_CARD_INSERT;
+ else
+ val &= ~F_SDH30_FORCE_CARD_INSERT;
+ sdhci_writel(host, val, F_SDH30_TEST);
+}
+
static int f_sdh30_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
@@ -25,6 +60,8 @@ static int f_sdh30_sdhci_probe(struct udevice *dev)
struct sdhci_host *host = dev_get_priv(dev);
int ret;
+ plat->data = (const struct f_sdh30_data *)dev_get_driver_data(dev);
+
ret = mmc_of_parse(dev, &plat->cfg);
if (ret)
return ret;
@@ -33,6 +70,9 @@ static int f_sdh30_sdhci_probe(struct udevice *dev)
host->mmc->dev = dev;
host->mmc->priv = host;
+ if (plat->data && plat->data->quirks)
+ host->quirks = plat->data->quirks;
+
ret = sdhci_setup_cfg(&plat->cfg, host, 200000000, 400000);
if (ret)
return ret;
@@ -41,18 +81,29 @@ static int f_sdh30_sdhci_probe(struct udevice *dev)
mmc_set_clock(host->mmc, host->mmc->cfg->f_min, MMC_CLK_ENABLE);
- return sdhci_probe(dev);
+ ret = sdhci_probe(dev);
+ if (ret)
+ return ret;
+
+ if (plat->data && plat->data->init)
+ plat->data->init(dev);
+
+ return 0;
}
static int f_sdh30_of_to_plat(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
host->name = strdup(dev->name);
host->ioaddr = dev_read_addr_ptr(dev);
host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
host->index = dev_read_u32_default(dev, "index", 0);
+ plat->enable_cmd_dat_delay =
+ dev_read_bool(dev, "socionext,enable-cmd-dat-delay");
+
return 0;
}
@@ -63,8 +114,19 @@ static int f_sdh30_bind(struct udevice *dev)
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
+static const struct f_sdh30_data f_sdh30_e51_data = {
+ .init = f_sdh30_e51_init,
+ .quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_SUPPORT_SINGLE,
+};
+
static const struct udevice_id f_sdh30_mmc_ids[] = {
- { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
+ {
+ .compatible = "fujitsu,mb86s70-sdhci-3.0",
+ },
+ {
+ .compatible = "socionext,f-sdh30-e51-mmc",
+ .data = (ulong)&f_sdh30_e51_data,
+ },
{ }
};
diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c
index 570d54cf9d8..cabb747fbbd 100644
--- a/drivers/mmc/ftsdc010_mci.c
+++ b/drivers/mmc/ftsdc010_mci.c
@@ -30,7 +30,7 @@
#include <syscon.h>
#include <linux/err.h>
-#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
+#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */
#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 0b7c0be8cbc..210703ea46b 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -3113,10 +3113,12 @@ int mmc_init_device(int num)
}
m = mmc_get_mmc_dev(dev);
- m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */
-
if (!m)
return 0;
+
+ /* Initialising user set speed mode */
+ m->user_speed_mode = MMC_MODES_END;
+
if (m->preinit)
mmc_start_init(m);
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index bf989a594f7..a80ad8329a3 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -211,7 +211,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
unsigned int stat = 0;
int ret = 0;
int trans_bytes = 0, is_aligned = 1;
- u32 mask, flags, mode;
+ u32 mask, flags, mode = 0;
unsigned int time = 0;
int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
ulong start = get_timer(0);
@@ -273,10 +273,12 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
/* Set Transfer mode regarding to data flag */
if (data) {
sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
- mode = SDHCI_TRNS_BLK_CNT_EN;
+
+ if (!(host->quirks & SDHCI_QUIRK_SUPPORT_SINGLE))
+ mode = SDHCI_TRNS_BLK_CNT_EN;
trans_bytes = data->blocks * data->blocksize;
if (data->blocks > 1)
- mode |= SDHCI_TRNS_MULTI;
+ mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN;
if (data->flags == MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
index 7ab4d949e74..b68594de373 100644
--- a/drivers/mmc/stm32_sdmmc2.c
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -25,6 +25,7 @@
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/iopoll.h>
+#include <power/regulator.h>
#include <watchdog.h>
struct stm32_sdmmc2_plat {
@@ -36,6 +37,9 @@ struct stm32_sdmmc2_plat {
struct gpio_desc cd_gpio;
u32 clk_reg_msk;
u32 pwr_reg_msk;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ bool vqmmc_enabled;
+#endif
};
struct stm32_sdmmc2_ctx {
@@ -572,6 +576,15 @@ static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_plat *plat)
plat->base + SDMMC_POWER);
/* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (plat->mmc.vqmmc_supply && !plat->vqmmc_enabled) {
+ if (regulator_set_enable_if_allowed(plat->mmc.vqmmc_supply, true))
+ dev_dbg(plat->mmc.dev, "failed to enable vqmmc-supply\n");
+ else
+ plat->vqmmc_enabled = true;
+ }
+#endif
}
#define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
@@ -598,13 +611,16 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev)
* clk_div > 0 and NEGEDGE = 1 => command and data generated on
* SDMMCCLK falling edge
*/
- if (desired && ((sys_clock > desired) ||
+ if (desired && (sys_clock > desired || mmc->ddr_mode ||
IS_RISING_EDGE(plat->clk_reg_msk))) {
clk = DIV_ROUND_UP(sys_clock, 2 * desired);
if (clk > SDMMC_CLKCR_CLKDIV_MAX)
clk = SDMMC_CLKCR_CLKDIV_MAX;
}
+ if (mmc->ddr_mode)
+ clk |= SDMMC_CLKCR_DDR;
+
if (mmc->bus_width == 4)
clk |= SDMMC_CLKCR_WIDBUS_4;
if (mmc->bus_width == 8)
@@ -672,6 +688,8 @@ static int stm32_sdmmc2_of_to_plat(struct udevice *dev)
if (ret)
return ret;
+ cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES);
+
ret = clk_get_by_index(dev, 0, &plat->clk);
if (ret)
return ret;